ADUC7023BCP6Z62I Analog Devices Inc, ADUC7023BCP6Z62I Datasheet - Page 51

• Manufacturer Part Number: ADUC7023BCP6Z62I
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCP6Z62I

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12 x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GP2PAR Register
Name
Address
Default value
Access
Function
Table 56. GPxPAR MMR Bit Descriptions
Bit
31
30 to 29
28
27
26 to 26
24
23
22 to 21
20
19
18 to 17
16
15
14 to 13
12
11
10 to 9
8
7
6 to 5
4
3
2 to 1
0
Table 57. GPIO Drive Strength Control Bits Descriptions
Control Bits Value
00
01
1x
GP2PAR
0xFFFFF44C
0x00000000
Read/write
GP2PAR programs the parameters for Port 0,
Port 1, and Port 2. Note that the GP2DAT
MMR must always be written after changing
the GP2PAR MMR.
Description
Reserved.
Drive strength Px.7
Pull-up disable Px.7.
Reserved.
Drive strength Px.6
Pull-up disable Px.6.
Reserved.
Drive strength Px.5
Pull-up disable Px.5.
Reserved.
Drive strength Px.4
Pull-up disable Px.4.
Reserved.
Drive strength Px.3
Pull-up disable Px.3.
Reserved.
Drive strength Px.2
Pull-up disable Px.2.
Reserved.
Drive strength Px.1
Pull-up disable Px.1.
Reserved.
Drive strength Px.0
Pull-up disable Px.0.
Description
Medium drive strength.
Low drive strength.
High drive strength.
Rev. B | Page 51 of 96
The drive strength bits can be written one time only after reset.
More writing to related bits has no effect on changing drive
strength. The GPIO drive strength and pull-up disable is not always
adjustable for the GPIO port. Some control bits cannot be changed
(see Table 58).
Table 58. GPxPAR Control Bits Access Descriptions
Bit
31
30 to 29
28
27
26 to 26
24
23
22 to 21
20
19
18 to 17
16
15
14 to 13
12
11
–0.1
–0.2
–0.3
–0.4
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0.5
0.4
0.3
0.2
0.1
–24
0
–24
Reserved
R/W
Reserved
R/W
Reserved
R/W
Reserved
R/W
Reserved
R/W
Reserved
R/W
R/W
R/W
R(b00)
R(b00)
Figure 37. Programmable Strength for High Level
Figure 38. Programmable Strength for Low Level
–18
GP0PAR
–18
–12
–12
LOAD CURRENT (mA)
LOAD CURRENT (mA)
–6
–6
Reserved
R/W
R/W
Reserved
R/W
R/W
Reserved
R(b00)
R/W
Reserved
R(b00)
R/W
Reserved
R(b00)
R/W
Reserved
GP1PAR
0
0
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
6
6
12
12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R(b00)
R/W
Reserved
R(b00)
R/W
Reserved
ADuC7023
18
18
GP2PAR
1
24
24