ADUC7060BCPZ32-RL Analog Devices Inc, ADUC7060BCPZ32-RL Datasheet - Page 65

• Manufacturer Part Number: ADUC7060BCPZ32-RL
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7060BCPZ32-RL

• Design Resources: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMERS
The ADuC706x features four general-purpose timer/counters.
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•
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The four timers in their normal mode of operation can be either
free running or periodic.
In free running mode, the counter decrements/increments from
the maximum or minimum value until zero/full scale and starts
again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register. Note that the
TxLD MMR should be configured before the TxCON MMR.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time that the value
of the counter reaches zero (if counting down) or full scale (if
counting up). An IRQ can be cleared by writing any value to the
clear register of the particular timer (TxCLRI).
Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
Timer3
Rev. B | Page 65 of 108
Table 78. Timer Event Capture
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Description
Reserved
Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
Timer3
Reserved
Reserved
Reserved
ADC
UART
SPI
XIRQ0
XIRQ1
I
I
PWM
XIRQ2 (GPIO IRQ2)
XIRQ3 (GPIO IRQ3)
2
2
C master
C slave
ADuC7060/ADuC7061