ADUM5202CRWZ Analog Devices Inc, ADUM5202CRWZ Datasheet - Page 4

• Manufacturer Part Number: ADUM5202CRWZ
• Description: DUAL-CHANNEL ISOLATOR W/INTEGRATED DC/DC
• Manufacturer: Analog Devices Inc
• Series: IsoPower®, iCoupler®r

Specifications of ADUM5202CRWZ

• Inputs - Side 1/side 2: 0/2
• Number Of Channels: 2
• Isolation Rating: 2500Vrms
• Voltage - Supply: 3.3V, 5V
• Data Rate: 25Mbps
• Propagation Delay: 45ns
• Output Type: Logic
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuM5200/ADuM5201/ADuM5202
Parameter
AC SPECIFICATIONS
1
2
3
4
5
6
7
The contributions of supply current values for all four channels are combined at identical data rates.
V
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the
Power Consumption
The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of its internal power consumption.
This current is available for driving external loads at the V
representing the maximum dynamic load conditions. Refer to the
I
Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built
into the detection threshold to prevent oscillations and noise sensitivity.
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
DD1(MAX)
ISO
Logic High Output Voltages
Logic Low Output Voltages
ADuM520xARWZ
ADuM520xCRWZ
For All Models
supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, data I/O channels draw additional current
Minimum Pulse Width
Minimum Pulse Width
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Codirectional Channels
Opposing-Directional Channels
at Logic High Output
at Logic Low Output
is the input current under full dynamic and V
Change vs. Temperature
section. The dynamic I/O channel load must be treated as an external load and be included in the V
7
7
PLH
PLH
− t
− t
PHL
PHL
|
|
Symbol
V
V
V
PW
t
PWD
t
t
PW
t
PWD
t
t
t
t
|CM
|CM
f
ISO
r
PHL
PSK
PSKCD
PHL
PSK
PSKCD
PSKOD
R
OAH
OAH
OAL
/t
load conditions.
, t
, t
F
, V
H
L
, V
, V
ISO
, t
|
|
PLH
PLH
OBL
PSKOD
OBH
OBH
pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load
Power Consumption
Min
V
V
V
V
1
25
25
25
DD1
ISO
DD1
ISO
− 0.3
− 0.5
− 0.3,
− 0.5,
Rev. 0 | Page 4 of 24
Typ
5.0
4.8
0.0
0.0
55
45
5
2.5
35
35
1.0
section for the calculation of available current at less than the maximum data rate.
Max
0.1
0.4
1000
100
40
50
50
40
60
6
15
6
15
Unit
V
V
V
V
ns
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
Test Conditions
I
I
I
I
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
magnitude = 800 V
V
magnitude = 800 V
ISO
Ox
Ox
Ox
Ox
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Ix
Ix
power budget.
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= −20 μA, V
= −4 mA, V
= 20 μA, V
= 4 mA, V
= V
= 0 V, V = 1000 V, transient
DD
or V
Ix
ISO
Ix
Ix
= V
Ix
= V
, V
= V
= V
CM
IxL
IxL
IxH
IxH
= 1000 V, transient