AM29F002BT-70JC Spansion Inc., AM29F002BT-70JC Datasheet - Page 20

• Manufacturer Part Number: AM29F002BT-70JC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29F002BT-70JC

• Memory Size: 2Mbit
• Memory Configuration: 256K X 8
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: PLCC
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD

WRITE OPERATION STATUS
T h e de v i c e p r ov i d es s ev e ra l b i ts to d e ter m in e t he
s tatus of a w ri te o per ation : D Q2 , D Q 3, D Q 5, D Q 6, and
D Q 7.
the fu nc tions o f the s e bits . D Q 7 a nd D Q 6 e ac h o ffer a
m e tho d fo r de ter m in ing w he th er a p ro gra m or e ras e
o pera tion is c om p lete o r in pro gre s s. T h es e thr ee bits
a re dis c us s e d fir s t.
DQ7: Data# Polling
T h e D a ta # Po l li n g b i t, D Q 7 , in d i c a te s to the h o s t
s y s te m w h ether an E m bed de d A lgo rithm is in pr ogr es s
o r c o m ple te d, or w he th er the dev i ce is in Er as e Su s -
p end . D a ta # Polli ng is v alid a fte r th e ris in g ed ge o f the
fin a l W E # p ul s e i n the pr og ra m o r er as e c om m a nd
s eq ue nc e.
D u rin g th e Em b ed ded P ro gram al go rithm , th e dev ic e
o utp u ts o n D Q 7 th e c o m p le m e n t o f th e d atu m p ro -
g ra m m ed to D Q 7 . T hi s D Q 7 s ta tus a ls o a pp li e s to
p r o g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n th e
E m bed de d P rogr am a lgo rithm is c o m ple te , the dev ic e
o utpu ts the d atum pr og ram m ed to D Q7 . T h e s ys te m
m us t pr ov ide th e pro gra m add res s to re ad v ali d s ta tu s
in for m atio n on D Q7 . If a pr ogra m a dd res s fall s w ithin a
p ro te c ted s ec to r, D a ta # Po lli ng o n D Q 7 is ac tiv e for
a ppr oxi m ately 2 µs , the n the d ev ic e re tu rn s to r ead ing
a rray data.
D u rin g the E m be dde d Era s e a lgo rithm , D ata# Pol ling
p rod uc e s a “0 ” on D Q 7. W he n the E m be dd ed E ras e
a lgor ithm is c o m ple te , or if th e dev ic e en te rs the E ras e
S us pe nd m o de, D ata# Po llin g pr odu c es a “1” o n D Q 7.
T hi s is ana log ou s to th e c om ple m ent/tr ue datu m ou tp ut
d es c r ibe d fo r the E m be dd ed P ro gra m alg or ithm : the
e ras e fun c ti on c ha ng es all the b its in a s ec to r to “1 ”;
p rio r to thi s, th e de vi c e outp uts th e “c om p le m en t,” or
“0 .” Th e s y s te m m us t p rov id e an a dd res s w ithin a ny of
th e s ec to rs s e le c ted for e ra s ur e to rea d v al id s tatu s
in for m atio n on D Q 7.
A fter an e ra s e c om m a nd s eq u en c e i s w ri tten , i f a l l
s e c t or s s e l ec ted fo r e ra s i n g a r e p r o tec te d, D at a#
Po lling o n D Q 7 is a c tiv e fo r a pp rox im atel y 10 0 µs , then
th e d e v ic e r etu r n s to r e ad i ng a rr ay d a ta. If n ot a l l
s el ec ted s ec tor s ar e pro te c ted, th e Em b ed ded E ras e
a lgor ithm er as es the u npr otec ted s ec tor s, an d ign ore s
the s e lec ted s ec tors tha t ar e pro te c te d.
W h en th e s y s tem d etec ts D Q 7 h as c ha ng ed fro m the
c om p lem e nt to tru e d ata, it c an rea d v ali d d ata a t D Q 7–
D Q 0 o n the
c a n c h an g e a s y nc hr o n ou s l y w i th D Q 0– D Q 6 w h i le
O utpu t En abl e (OE #) is as s er ted lo w.
C h arac ter is ti cs ”
1 8
Ta ble 6
fo llowi ng
a nd the fol low in g s ub s ec tion s d es c ri be
il lus trates th is .
rea d c y c les . T his is be ca us e D Q7
F ig ure 13
A m 29 F 002 B /A m 29 F 00 2N B
in
“ AC
Ta ble 6
F i gur e 4
N otes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because
No
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
DQ7 can change simultaneously with DQ5.
s h ow s the o utpu ts fo r D ata# Po llin g on D Q 7.
F ig u r e 4.
s how s th e D ata# Po llin g alg ori th m .
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
D a ta# Po llin g A lg o rith m
Yes
Yes
PASS