AM29LV160DT-120EI Spansion Inc., AM29LV160DT-120EI Datasheet - Page 10

• Manufacturer Part Number: AM29LV160DT-120EI
• Description: IC,EEPROM,NOR FLASH,1MX16/2MX8,CMOS,TSSOP,48PIN,PLASTIC
• Manufacturer: Spansion Inc.

Specifications of AM29LV160DT-120EI

• Rohs Compliant: NO

Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
b o t h s t a n d a r d a n d U n l o ck B y p a s s c o m m a n d
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.
I
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
10
CC2
in the DC Characteristics table represents the ac-
IL
, and OE# to V
IH
.
Am29LV160D
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device requires
standard access time (t
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, I
sents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
Characteristics table represents the automatic sleep
mode current specification.
IH
CC
.) If CE# and RESET# are held at V
0.3 V, the device will be in the standby mode, but
CE
) for read access when the
CC3
IH
and I
CC4
, but not within
CC
CC4
in the DC
ACC
repre-
0.3 V.
+ 30
CC