CAT5261YI-50-T2 ON Semiconductor, CAT5261YI-50-T2 Datasheet - Page 8

• Manufacturer Part Number: CAT5261YI-50-T2
• Description: DPP NV, DUAL 256 TAP, SPI
• Manufacturer: ON Semiconductor

Specifications of CAT5261YI-50-T2

• Lead Free Status / Rohs Status: Compliant

Instruction and Register Description
Device Type / Address Byte
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5261 are fixed at
0101[B] (refer to Figure 4).
− A0, are the internal slave address and must match the
physical device address which is defined by the state of the
A1 − A0 input pins for the CAT5261 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent by the
master executes the instruction. The A1 − A0 inputs can be
actively driven by CMOS input signals or tied to V
V
be set to 0.
SS
The first byte sent to the CAT5261 from the master/
The two least significant bits in the slave address byte, A1
HOLD
. The remaining two bits in the device address byte must
SCK
CS
SO
(MSB)
(MSB)
ID3
I3
0
ID2
I2
1
Device Type
Identifier
Instruction
Opcode
t
HD
t
CD
ID1
Figure 4. Identification Byte Format
I1
Figure 5. Instruction Byte Format
t
HZ
0
Figure 3. HOLD Timing
http://onsemi.com
CC
ID0
I0
or
1
8
HIGH IMPEDANCE
Instruction Byte
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I3 − I0.
The R1 and R0 bits point to one of the four data registers of
each associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format is
shown in Figure 5.
Table 12. DATA REGISTER SELECTION
A3
R1
The next byte sent to the CAT5261 contains the
Data Register
t
HD
Selection
Data Register Selected
A2
R0
Slave Address
DR0
DR1
t
CD
t
LZ
A1
WCR/Pot Selection
P1
(LSB)
(LSB)
A0
P0
R1
0
0
R0
0
1