CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 17

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

DS761F2
5.2.2
If CLK_IN is removed and then re-applied within t
continues while the PLL re-acquires lock (see
moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only
for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this
time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous
throughout the missing CLK_IN period including the time while the PLL re-acquires lock.
Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128
Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter
transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL
input directly to the PLL output without attenuation. In some applications it is desirable to have a very low
minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others
it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the
PLL without attenuation.
ClkSkipEn=1
ClkOutUnl=0 or 1
Referenced Control
ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 31
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32
PLL_OUT
UNLOCK
CLK_IN
Register Location
ClkSkipEn=0
ClkOutUnl=0
Figure 15. CLK_IN removed for < t
PLL_OUT
UNLOCK
CLK_IN
t
CS
Figure
CS
15). When ClkSkipEn is disabled and CLK_IN is re-
, the ClkSkipEn bit determines whether PLL_OUT
ClkSkipEn=0
ClkOutUnl=1
Lock Time
PLL_OUT
UNLOCK
t
CS
CLK_IN
CS
= invalid clocks
Lock Time
CS2000-CP
t
CS
17