Advance Product Information
Features
General Description
The CS2300-02 is an extremely versatile system clock-
ing device that utilizes a programmable phase lock loop.
The CS2300-02 is based on a hybrid analog-digital PLL
architecture comprised of a unique combination of a
Delta-Sigma Fractional-N Frequency Synthesizer and a
Digital PLL. This architecture allows for generation of a
low-jitter clock relative to an external noisy synchroniza-
tion clock with frequencies as low as 750 kHz. The
CS2300-02 is a CS2300-OTP device that has been pre-
configured at the factory. There are three hardware con-
figuration pins available for mode and feature selection.
Clock Multiplier / Jitter Reduction
Internal LCO Reference Clock
128 Hz Loop Filter Bandwidth
Selectable Multiplication Factors
Output Enable Pin
Lock Indicator
Minimal Board Space Required
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http://www.cirrus.com
Frequency Reference
1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO
750 kHz to 30 MHz
Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 750 kHz to 30 MHz Clock
Source
1x, 2x, 4x, and 8x
No External Analog Loop-filter
Components
Ratio Selection
0.1 µF
FILTP
FILTN
M1
M0
CLK_IN
M[1:0]
00=1x
01=2x
10=4x
11=8x
LCO
Output to Input
Clock Ratio
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2008
Frequency Synthesizer
(All Rights Reserved)
128 Hz BW Digital PLL
& Fractional N Logic
Fractional-N
Ordering Information
The CS2300-02 is available in a 10-pin MSOP package
in Commercial (-10°C to +70°C) grade. Customer de-
velopment kits are also available for custom device
prototyping and device evaluation. Please see
ing Information” on page 2
Pin-Out Diagram
Hardware Controls Settings
CLK_OUT
N
CLK_IN
LOCK
GND
M1
0
0
1
1
VD
OUT_EN
0
1
1
2
3
4
5
M0
0
1
0
1
CLK_OUT
OUT_EN
for complete details.
LOCK
CS2300-02
GND
VD
High Impedance
CLK_OUT
PLL_OUT
1x CLK_IN
2x CLK_IN
4x CLK_IN
8x CLK_IN
0.1 µF
Enabled
Output
Enable/Disable
10
PLL Lock
Indicator
6 MHz to 75 MHz
PLL Output
9
8
7
6
1 µF
February '08
M1
M0
OUT_EN
FILTN
FILTP
PS855A1
3.3 V
“Order-