CS2300CP-DZZR Cirrus Logic Inc, CS2300CP-DZZR Datasheet - Page 27

• Manufacturer Part Number: CS2300CP-DZZR
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1406-2; CS2300CP-DZZR

DS843F1
8.6
8.6.1
8.6.2
8.6.3
ClkSkipEn
7
Function Configuration 1 (Address 16h)
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
Note:
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
Note:
fore, the pin polarity is defined relative to the unlock condition.
Enable Device Configuration Registers 3 (EnDevCfg3)
This bit, in conjunction with EnDevCfg1 and EnDevCfg2, configures the device for control port mode.
These EnDevDfg bits can be set in any order and at any time during the control port access sequence,
however they must all be set before normal operation can occur.
Note:
Port” on page
ClkSkipEn
0
1
Application:
AuxLockCfg
0
1
Application:
EnDevCfg3
0
1
Application:
AuxLockCfg
f
AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
EnDevCfg1 and EnDevCfg2 must also be set to enable control port mode. See
CLK_IN
6
20.
must be < 80 kHz and re-applied within
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 13
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 19
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 20
Reserved
5
EnDevCfg3
4
Reserved
3
20
ms to use this feature.
Reserved
2
Reserved
1
“SPI / I²C Control
CS2300-CP
Reserved
0
27