CS42435-DMZR Cirrus Logic Inc, CS42435-DMZR Datasheet - Page 27

• Manufacturer Part Number: CS42435-DMZR
• Description: IC,Soundcard Circuits,CMOS,QFP,52PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42435-DMZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS685F3
5.2
5.2.1
5.2.2
DAC Auto-Mute
Status Interrupt
Analog Inputs
5.2.1.1
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode.
5.2.1.2
Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.
Figure 9 on page 27
ended signals on all inputs, AIN1-AIN4. See
filters.
For single-ended operation on ADC1-ADC2 (AIN1 to AIN4), the ADCx_SINGLE bit in the register
Control & DAC De-Emphasis (Address 05h)” on page 42
page 48
The gain/attenuation of the signal can be adjusted for each AINx independently through the
Control (Address 11h-14h)” on page
puts above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, re-
spectively, and cause the ADC Overflow bit in the register
to be set to a ‘1’.
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the
Function
for required external components).
Hardware Mode
Software Mode
3.9 V
1.1 V
3.9 V
1.1 V
Table 2. Hardware Configurable Settings (Continued)
2.5 V
2.5 V
shows the full-scale analog input levels. The CS42435 also accommodates single-
(AINx+) - (AINx-) = 5.6 V
Full-Scale Differential Input Level =
Hardware Mode Feature Summary
Figure 9. Full-Scale Input
Default Configuration
45. The ADC output data is in 2’s complement binary format. For in-
PP
Enabled
= 1.98 V
N/A
“ADC Input Filter” on page 48
RMS
“Status (Address 19h) (Read Only)” on page 46
must be set appropriately (see
AINx-
AINx+
Hardware Control
VA
-
-
for the recommended input
5.0 V
-
-
“AINX Volume
CS42435
Figure 20 on
Note
“ADC
27