CS42448-CQZR Cirrus Logic Inc, CS42448-CQZR Datasheet - Page 28

• Manufacturer Part Number: CS42448-CQZR
• Description: IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

28
4.3.2
4.3.3
4.3.4
4.3.3.1
When the device is initially powered up, the audio outputs, AOUTxx, are clamped to VQ which is initially
low. After the RST pin is brought high and MCLK is applied, the outputs begin to ramp with VQ towards
the nominal quiescent voltage. This ramp takes approximately 400 ms to complete. The gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the qui-
escent DC voltage. Once valid DAC_LRCK, DAC_SCLK and DAC_SDINx are applied, audio output be-
gins approximately 2000 sample periods later.
4.3.3.2
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this, the PDN bit in register
must be set to ‘1’ for a period of about 250 ms before removing power. During this time, voltage on VQ
and the audio outputs discharge gradually to AGND. If power is removed before this 250 ms time period
has passed, a transient will occur when the VA supply drops below that of VQ. There is no minimum time
for a power cycle. Power may be re-applied at any time.
Output Transient Control
The CS42448 uses Popguard technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended single-
supply converters when it is implemented with external DC-blocking capacitors connected in series with
the audio outputs. To make best use of this feature, it is necessary to understand its operation. See
guard” on page 28
A Mute Control pin is also available for use with an optional mute circuit to mask output transients on the
analog outputs. See
When changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present
on DAC_SDINx for at least 10 LRCK samples before the change is made. During the clocking change,
the DAC outputs will always be in a zero-data state. If no zero audio is present at the time of switching, a
slight click or pop may be heard as the DAC output automatically goes to its zero-data state.
Popguard
Mute Control
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The use of ex-
ternal mute circuits is not mandatory, but may be desired for designs requiring the absolute minimum in
extraneous clicks and pops.
MUTEC is in high-impedance mode during power up or when the CS42448 enters Power-Down Mode by
setting the PDN bit in the register
Down Mode, the pin can be controlled by the user via the control port (see
1Bh)” on page
puts, when all DAC outputs are muted, or when serial port clock errors occur.
To prevent large transients on the output, it is recommended to mute the DAC outputs before the Mute
Control pin is asserted.
Power-Up
Power-Down
52) or automatically asserted to the active state when zero data is present on all DAC in-
for details.
“Mute Control” on page 28
“Power Control (Address 02h)” on page 42
for details.
“Power Control (Address 02h)” on page 42
“MUTEC Pin Control (Address
to a ‘1’. Once out of Power-
CS42448
DS648F3
“Pop-