CS42888-CQZ Cirrus Logic Inc, CS42888-CQZ Datasheet - Page 44

• Manufacturer Part Number: CS42888-CQZ
• Description: IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42888-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Adcs: 2
• No. Of Dacs: 4
• No. Of Input Channels: 8
• No. Of Output Channels: 4
• Adc / Dac Resolution: 24bit
• Ic Interface Type: Serial
• Supply Voltage Range: 3.14V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1183

44
6.5.4
6.6
6.6.1
ADC1-2_HPF
FREEZE
7
ADC Control & DAC De-Emphasis (Address 05h)
ADC Digital Interface Format (ADC_DIF[2:0])
Default = 110
Function:
These bits select the digital interface format used for the ADC serial port. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options
are detailed in the section
Interface Channel Allocations,” on page
Note:
ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset
value will be frozen and continue to be subtracted from the conversion result. See
Characteristics” on page
DAC_DIF2
ADC_DIF2 ADC_DIF1 ADC_DIF0
0
1
1
1
1
0
0
0
0
1
1
1
1
Reserved
The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.
6
DAC_DIF1
1
0
0
1
1
0
0
1
1
0
0
1
1
DAC_DEM
5
13.
“CODEC Digital Interface Formats” on page
DAC_DIF0
Table 12. DAC Digital Interface Formats
Table 13. ADC Digital Interface Formats
0
1
0
1
0
1
0
1
1
0
1
0
1
SINGLE
ADC1
4
33.
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 24-bit data
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
SINGLE
ADC2
Description
Description
3
Reserved
2
30. Refer to
Reserved
Format
Format
1
Table 9, “Serial Audio
0
1
2
3
4
5
6
-
3
4
5
6
-
“ADC Digital Filter
CS42888
Figure 15
Figure 14
Figure 16
Figure 16
Figure 17
Figure 18
Figure 19
Figure 16
Figure 17
Figure 18
Figure 19
Reserved
Figure
Figure
DS717F2
0
-
-