CS4299-BQZR Cirrus Logic Inc, CS4299-BQZR Datasheet - Page 7

• Manufacturer Part Number: CS4299-BQZR
• Description: IC AC97 Codec With SRC
• Manufacturer: Cirrus Logic Inc

DS319-BQPP2
AC ’97 SERIAL PORT TIMING
AVdd = 5.0 V, DVdd = 3.3 V; C
RESET Timing
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
1st SYNC active to CODEC READY set
Vdd stable to Reset inactive
Clocks
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter (depends on XTAL_IN source)
BIT_CLK high pulse width
BIT_CLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Data Setup and Hold
Output Propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input Signal rise time
Input Signal fall time
Output Signal rise time
Output Signal fall time
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T
Rising edge of RESET# to Hi-Z delay
Parameter
L
= 55 pF load.
Standard test conditions unless otherwise noted: T
(Note 4)
(Note 4)
(Note 4)
T
T
T
T
T
T
T
T
sync_period
T
Symbol
T
T
T
clk_period
s2_pdown
T
sync_high
sync_low
T
setup2rst
sync2crd
sync_pr4
vdd2rst#
sync2clk
clk_high
T
T
F
T
T
clk_low
rst_low
T
rst2clk
F
T
isetup
T
orise
sync
ihold
irise
ofall
ifall
clk
off
co
162.8
Min
100
1.0
1.0
36
36
10
15
0
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
-
12.288
40.0
62.5
81.4
40.7
40.7
20.8
19.5
Typ
285
1.3
.28
48
12
4
4
-
-
-
-
-
-
-
-
-
-
CS4299-BQ
ambient
CS4299-BQ
Max
750
1.0
45
45
25
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= 25° C,
MHz
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7