CS4350-CZZR Cirrus Logic Inc, CS4350-CZZR Datasheet - Page 32

• Manufacturer Part Number: CS4350-CZZR
• Description: IC 105dB 192kHz DAC W/PLL
• Manufacturer: Cirrus Logic Inc

Specifications of CS4350-CZZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 290mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1517 - BOARD EVAL FOR CS4350 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32
8.4
8.4.1
8.4.2
8.4.3
AMUTE
7
1
Mute Control - Register 04h
Auto-Mute (AMUTE) Bit 7
Function:
When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. De-
tection and muting is done independently for each channel. The quiescent voltage on the output will be
retained and the Mute Control pin will go active during the mute period.
When set to 0, this function is disabled
AMUTEC = BMUTEC (MUTEC A=B) Bit 5
Function:
When set to 0 (default), the AMUTEC and BMUTEC pins operate independently.
When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an
AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins go active only
when the requirements for both AMUTEC and BMUTEC are valid.
Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3
Function:
When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will
be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross
bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any
ramping due to the soft and zero cross function.
When set to 0 (default), this function is disabled.
ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0
Reserved
1
1
1
1
1
1
1
1
6
0
0
0
0
0
1
1
1
1
MUTEC A=B
5
0
0
0
1
1
0
0
1
1
MUTE_A
Table 4. ATAPI Decode
4
0
0
1
0
1
0
1
0
1
MUTE_B
3
0
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
AOUTA
aL
aL
aL
aL
Reserved
2
0
b[(L+R)/2]
b[(L+R)/2]
AOUTB
MUTE
MUTE
Reserved
bR
bR
bL
bL
1
0
CS4350
Reserved
DS691F1
0
0