CS4525-CNZR Cirrus Logic Inc, CS4525-CNZR Datasheet - Page 37

IC PWM Controller+power Stage

CS4525-CNZR

Manufacturer Part Number
CS4525-CNZR
Description
IC PWM Controller+power Stage
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Type
Class Dr
Datasheet

Specifications of CS4525-CNZR

Output Type
2-Channel (Stereo) or 4-Channel (Quad)
Max Output Power X Channels @ Load
30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
Voltage - Supply
8 V ~ 18 V
Features
ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
Mounting Type
Surface Mount
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1586 - REFERENCE BOARD FOR CS4525 PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4525-CNZR
Manufacturer:
CIRRUSLOGICINC
Quantity:
20 000
DS726PP3
6.1.4.10 Peak Signal Limiter
When enabled, the limiter monitors the digital output following the volume control block, detects when
peak levels exceed a selectable maximum threshold level and lowers the volume at a programmable at-
tack rate until the signal peaks fall below the maximum threshold. When the signal level falls below a se-
lectable minimum threshold, the volume returns to its original level (as determined by the individual and
master volume control registers) at a programmable release rate. Attack and release rates are affected
by the soft ramp/zero cross settings and sample rate, Fs.
Recommended settings: Best limiting performance may be realized with the fastest attack and slowest
release setting with soft ramp enabled in the control registers. Use the “minimum” bits to set a threshold
slightly below the maximum threshold to cushion the sound as the limiter attacks and releases.
By default, the limiter affects all channels when the maximum threshold is exceeded on any single chan-
nel. This default functionality is designed to keep all output channels at the same volume level while the
limiter is in use. This behavior can be disabled by clearing the LimitAll bit in the Limiter Cfg 1 register.
(after Limiter)
Max[2:0]
Limiter
Output
Input
Volume
Figure 17. Peak Signal Detection & Limiting
ARate[5:0]
Attack/Release Sound
Attack/Release Sound
Cushion
Cushion
Min[2:0]
RRate[5:0]
CS4525
37

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