CS5345-DQZR Cirrus Logic Inc, CS5345-DQZR Datasheet - Page 28

• Manufacturer Part Number: CS5345-DQZR
• Description: IC,Data Acquisition Signal Conditioner,6-CHANNEL,24-BIT,CMOS,QFP,48PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

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4.8
4.9
4.10
4.11
Interrupts and Overflow
The CS5345 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see
open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with
multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external
pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see
Status - Address 0Dh” on page
each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of level-
sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, de-
pending on the needs of the equipment designer.
The CS5345 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these
conditions do not need to be unmasked for proper operation of the OVFL pin.
Reset
When RESET is low, the CS5345 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET is high, the control port becomes operation-
al, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Pow-
er Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, SDOUT will be automatically muted.
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the
CS5345s in the system. If only one master clock source is needed, one solution is to place one CS5345 in
Master Mode, and slave all of the other CS5345s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS5345 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5345 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized.
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
35). Each source may be masked off through mask register bits. In addition,
“Active High/Low (Bit 0)” on page
Figure 7
35). When configured as active low
shows the recommended power ar-
CS5345
DS658F2
“Interrupt