CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 16

• Manufacturer Part Number: CS5368-DQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

DS624A1
SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a 3 pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; C
Notes:
OVERFLOW TIMEOUT
Logic "0" = GND = 0 V; Logic "1" = VLS; C
Sample Rates
SCLK Frequency
SCLK Period
SCLK Duty Cycle
FS setup
FS hold
FS width
SDOUT setup
SDOUT hold
OVFL time-out on overrange condition
1. TDM Quad-Speed Mode only specified to operate correctly at VLS ≥ 3.14 V.
2. In Master mode, the SCLK/LRCK ratio is fixed at 256. In Slave Mode, the SCLK/RCLK ratio can be set
SDOUT
SCLK
according to preference. However, chip performance is guaranteed only when using the ratios in
4.6.9 Master and Slave Clock Frequencies on page
FS
2
data
Parameter
Parameter
Double-Speed Mode
Quad-Speed Mode
Single-Speed Mode
before SCLK rising
before SCLK rising
after SCLK rising
after SCLK rising
t
PERIOD
in SCLK cycles
1/(256*54 kHz)
Fs = 44.1 kHz
Fs = 192 kHz
L
L
= 20 pF, timing threshold is 50% of VLS.
= 15 pF, timing threshold is 50% of VLS.
Table 1. Overflow Timeout
t
Figure 3. TDM Timing
SET UP2
t
SET UP1
1
data
Symbol
Symbol
t
t
t
t
t
PERIOD
SETUP1
SETUP2
t
t
HOLD1
HOLD2
HIGH1
HIGH2
new frame
t
-
-
-
HOLD2
29.
t
HIGH1
t
HIGH2
72.3
Min
Min
108
54
30
20
20
10
10
2
3
-
-
-
-
(2
256*Fs
17
2972
Typ
Typ
683
-1)/Fs
-
-
-
-
-
-
-
-
-
-
data
t
HOLD1
Max
Max
108
216
250
54
70
-
-
-
-
-
-
-
-
-
CS5368
Section
Unit
Unit
kHz
kHz
kHz
Hz
ms
ms
ms
ns
ns
ns
ns
ns
%
-
19