CS5463-ISZR Cirrus Logic Inc, CS5463-ISZR Datasheet - Page 14

• Manufacturer Part Number: CS5463-ISZR
• Description: Single Phase, Bidirectional Power/Energy
• Manufacturer: Cirrus Logic Inc
• Type: Bidirectional Power/Energy ICr

Specifications of CS5463-ISZR

• Input Impedance: 30 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 0.8V
• Voltage - I/o Low: 0.2V
• Current - Supply: 2.9mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Meter Type: Single Phase
• Output Voltage Range: 2.4 V to 2.6 V
• Output Current: 100 mA
• Input Voltage Range: 3.135 V to 5.25 V
• Input Current: 25 nA
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1553 - BOARD EVAL & SOFTWARE CS5463 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4. THEORY OF OPERATION
The CS5463 is a dual-channel analog-to-digital convert-
er (ADC) followed by a computation engine that per-
forms
conversion. The data flow for the voltage and current
channel measurement and the power calculation algo-
rithms are depicted in Figure 3 and 4, respectively.
The analog inputs are structured with two dedicated
channels, Voltage and Current , then optimized to simpli-
fy interfacing to various sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is sub-
ject to a gain of 10x. A second-order delta-sigma modu-
lator samples the amplified signal for digitization.
Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to two selectable gains of the program-
mable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
4.1 Digital Filters
The decimating digital filters on both channels are Sinc
filters followed by 4th-order IIR filters. The single-bit
data is passed to the low-pass decimation filter and out-
put at a fixed word rate. The output word is passed to an
optional IIR filter to compensate for the magnitude roll
off of the low-pass filtering operation.
An optional digital high-pass filter ( HPF in Figure 3) re-
moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
14
CURRENT
VOLTAGE
power
x10
PGA
2nd Order
Modulator
Modulator
calculations
4th Order
PC6 PC5 PC4 PC3 PC2 PC1 PC0
∆Σ
∆Σ
Configuration Register *
DELAY
REG
SINC 3
6
and
Figure 3. Data Measurement Flow Diagram.
SINC 3
DELAY
Digital Filter
REG
Digital Filter
energy-to-pulse
SYS
X
X
Gain
*
DELAY
DELAY
REG
REG
2322
...
Operational Modes Register *
XVDEL XIDEL
8
IIR
IIR
3
7
from the calculated V
ent power.
When the optional HPF in either channel is disabled, an
all-pass filter (APF) is implemented. The APF has an
amplitude response that is flat within the channel band-
width and is used for matching phase in systems where
only one HPF is engaged.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC off-
set adjustment and a gain calibration (See Section 7.
System Calibration
surement is available by reading the instantaneous volt-
age and current registers.
The Root Mean Square ( RMS in Figure 4) calculations
are performed on N instantaneous voltage and current
samples, V
count), using the formula:
and likewise for V
cessible by register reads, which are updated once ev-
ery cycle count (referred to as a computational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-
ure 3). The product is then averaged over N conver-
sions to compute active power and is used to drive
energy pulse output E1. Energy output E2 is selectable,
providing an energy sign or a pulse output that is pro-
portional to the apparent power. Energy output E3
+
+
V
I
VHPF
DCoff
DCoff
Σ
Σ
6
+
+
*
*
IHPF
V
I
5
gn
gn
X
X
*
*
IIR
4
n
HPF
APF
APF
HPF
HPF
3
and I
2
1
0
RMS
n
I RMS
, respectively (where N is the cycle
on page 37). The calibrated mea-
X
RMS
, using V
V *
I *
=
and I
ε
P *
*
-------------------- -
n
N 1
∑
RMS
n
=
–
N
. I
2π
0
X
X
RMS
* DENOTES REGISTER NAME.
I n
as well as the appar-
+
Σ
and V
+
∫
CS5463
RMS
DS678F2
X
are ac-
V
Q *
Q
*