CY7C025AV-25AXC Cypress Semiconductor Corp, CY7C025AV-25AXC Datasheet - Page 5

• Manufacturer Part Number: CY7C025AV-25AXC
• Description: IC,SRAM,8KX16,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C025AV-25AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (8K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2095; CY7C025AV-25AXC

Pin Definitions
Architecture
The
CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and
16K words of 16 and 18 bits each of dual-port RAM cells, IO and
address lines, and control signals (CE, OE, RW). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes and reads to the same
location, a BUSY pin is provided on each port. Two Interrupt (INT)
pins can be used for port to port communication. Two Semaphore
(SEM) control pins are used for allocating shared resources. With
the M/S pin, the devices can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). They also have an
automatic power down feature controlled by CE. Each port has its
own output enable control (OE), which enables data to be read from
the device.
Functional Description
The
CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and
16K ×16/18 dual port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory. The devices can be used as standalone
16 or18-bit dual port static RAMs or multiple devices can be
combined to function as a 32 or 36-bit or wider master and slave
dual port static RAM. An M/S pin is provided for implementing 32 or
36-bit or wider memory applications. It does not need separate
master and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual port video and graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
Document #: 38-06052 Rev. *M
Left Port
CE
R/W
OE
A
IO
SEM
UB
LB
INT
BUSY
M/S
V
GND
NC
0L
CC
0L
L
L
L
L
–A
L
L
–IO
L
L
13L
17L
CY7C024AV/024BV/025AV/026AV
CY7C024AV/024BV/025AV/026AV
Right Port
CE
R/W
OE
A
IO
SEM
UB
LB
INT
BUSY
0R
0R
R
R
R
R
R
–A
R
–IO
R
R
13R
17R
Chip Enable
Read and Write Enable
Output Enable
Address (A
Data Bus Input and Output
Semaphore Enable
Upper Byte Select (IO
Lower Byte Select (IO
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
0
and
and
–A
11
for 4K devices; A
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared latches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE) pin.
The
CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin
Quad Flat Pack (TQFP) and 100-pin TQFP.
Write Operation
Data must be set up for a duration of t
of RW to guarantee a valid write. A write operation is controlled
by either the RW pin (see
Figure 9
tions are summarized in
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the data
read is not deterministic. Data is valid on the port t
data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
asserted. If the user wants to access a semaphore flag, then the
SEM pin and OE must be asserted.
Interrupts
The upper two memory locations are for message passing. The
highest
CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
8
0
–IO
–IO
15
7
CY7C024AV/024BV/025AV/026AV
on page 12). Required inputs for non-contention opera-
for x16 devices; IO
for x16 devices; IO
Description
memory
CY7C024AV/024BV/025AV/026AV
0
CY7C0241AV/0251AV/036AV
–A
12
for 8K devices; A
Table 1
Figure 8
location
0
9
–IO
ACE
–IO
8
on page 7.
17
on page 12) or the CE pin (see
after CE or t
for x18 devices)
for x18 devices)
SD
0
–A
(FFF
before the rising edge
13
for 16K)
DOE
DDD
Page 5 of 20
for
after OE is
after the
and
the
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