CY7C027-20AXC Cypress Semiconductor Corp, CY7C027-20AXC Datasheet - Page 10
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CY7C027-20AXC
Manufacturer Part Number
CY7C027-20AXC
Description
CY7C027-20AXC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C028-15AXC.pdf
(19 pages)
Specifications of CY7C027-20AXC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
512K (32K x 16)
Speed
20ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2098
CY7C027-20AXC
CY7C027-20AXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C027-20AXC
Manufacturer:
CY
Quantity:
67
Company:
Part Number:
CY7C027-20AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C027-20AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06042 Rev. *F
Notes
CE
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t
30. t
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
32. To access RAM, CE = V
33. To access upper byte, CE = V
34. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
To access lower byte, CE = V
[32,33]
HA
[32,33]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
IL
.
IL
Figure 8. Write Cycle No. 2: CE Controlled Timing
t
t
, LB = V
, UB = V
SA
SA
Figure 7. Write Cycle No. 1: R/W Controlled Timing
NOTE 35
(continued)
SCE
IH
.
IL
or t
IL
SD
, SEM = V
, SEM = V
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM and a LOW UB or LB.
t
HZWE
IH
IH
.
.
[34]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[31]
t
t
SD
SD
PWE
or (t
[28, 29, 30, 34, 35]
HZWE
t
t
HA
HA
[28, 29, 30, 31]
t
t
+ t
HD
HD
t
SD
LZWE
) to allow the I/O drivers to turn off and data
t
HZOE
[34]
NOTE 35
CY7C027/028
CY7C037/038
Page 10 of 19
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