CY7C027V-15AXCT Cypress Semiconductor Corp, CY7C027V-15AXCT Datasheet - Page 11
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CY7C027V-15AXCT
Manufacturer Part Number
CY7C027V-15AXCT
Description
CY7C027V-15AXCT
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C027V-15AXC.pdf
(22 pages)
Specifications of CY7C027V-15AXCT
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
512K (32K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C027V-15AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06078 Rev. *D
Notes
CE
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t
30. t
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
32. To access RAM, CE = V
33. To access upper byte, CE = V
34. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
the bus for the required t
To access lower byte, CE = V
[32,33]
HA
[32,33]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
SD
IL
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
, SEM = V
IL
, LB = V
IL
, UB = V
t
t
SA
SA
Figure 7. Write Cycle No. 1: R/W Controlled Timing
NOTE 35
Figure 8. Write Cycle No. 2: CE Controlled Timing
(continued)
IH
SCE
IL
.
, SEM = V
IL
or t
, SEM = V
PWE
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
IH
t
HZWE
.
[34]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[31]
PWE
t
t
SD
SD
or (t
HZWE
+ t
SD
t
t
) to allow the I/O drivers to turn off and data to be placed on
HA
HA
[28, 29, 30, 36]
[28, 29, 30, 31]
t
t
HD
HD
t
LZWE
CY7C027V/027AV/028V
CY7C037AV/038V
t
HZOE
NOTE 35
[34]
Page 11 of 22
PWE
.
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