CY7C027V-25AXC Cypress Semiconductor Corp, CY7C027V-25AXC Datasheet - Page 5

• Manufacturer Part Number: CY7C027V-25AXC
• Description: IC,SRAM,32KX16,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C027V-25AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 512K (32K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2100; CY7C027V-25AXC

Pin Definitions
Architecture
The CY7C027V/027AV/028V and CY7037AV/038V consist of an
array of 32K and 64K words of 16 and 18 bits each of dual-port
RAM cells, I/O and address lines, and control signals (CE, OE,
R/W). These control pins permit independent access for reads or writes
to any location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two interrupt (INT)
pins can be utilized for port-to-port communication. Two semaphore
(SEM) control pins are used for allocating shared resources. With the
M/S pin, the devices can function as a master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The devices also have an
automatic power down feature controlled by CE. Each port is provided
with its own output enable control (OE), which allows data to be read
from the device.
Functional Description
The CY7C027V/027AV/028V and CY7037AV/038V are low
power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various
arbitration schemes are included on the devices to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as stand-alone 16/18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32/36-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 32/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the other
port. The interrupt flag (INT) permits communication between ports or
systems by means of a mail box. The semaphores are used to pass a
Document #: 38-06078 Rev. *D
CE
R/W
OE
A
I/O
SEM
UB
LB
INT
BUSY
M/S
V
GND
NC
0L
CC
L
0L
0L
L
L
–A
L
L
L
–I/O
, CE
L
15L
Left Port
17L
1L
CE
R/W
OE
A
I/O
SEM
UB
LB
INT
BUSY
0R
R
0R
0R
R
R
R
–A
R
R
, CE
–I/O
R
15R
Right Port
17R
1R
Chip Enable (CE is LOW when CE
Read/Write Enable
Output Enable
Address (A
Data bus input/output (I/O
Semaphore Enable
Upper byte select (I/O
Lower byte select (I/O
Interrupt flag
Busy flag
Master or Slave select
Power
Ground
No connect
0
–A
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The
available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of t
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see
for non-contention operations are summarized in
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
the user wishes to access a semaphore flag, then the SEM pin must be
asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/037AV/027AV, FFFF for the CY7C028V/38V) is the
mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027AV/037AV, FFFE for the
CY7C028V/38V) is the mailbox for the left port. When one port
writes to the other port’s mailbox, an interrupt is generated to the
owner. The interrupt is reset when the owner reads the contents
of the mailbox. The message is user defined.
14
for 32K; A
CY7C027V/027AV/028V
8
0
–I/O
–I/O
0
–I/O
15
7
0
–A
Figure
for x16 devices; I/O
for x16 devices; I/O
15
15
Description
for x16 devices; I/O
for 64K devices)
0
7) or the CE pin (see
 V
ACE
CY7C027V/027AV/028V
IL
after CE or t
and CE
CY7C037AV/038V
and
0
1
9
–I/O
–I/O
V
SD
DOE
0
8
Figure
CY7037AV/038V
–I/O
IH
17
before the rising edge of
for x18 devices)
)
after OE is asserted. If
for x18 devices)
Table
17
8). Required inputs
for x18)
1.
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DDD
after
are
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