CY7C0831AV-133AXI Cypress Semiconductor Corp, CY7C0831AV-133AXI Datasheet - Page 17

CY7C0831AV-133AXI

CY7C0831AV-133AXI

Manufacturer Part Number
CY7C0831AV-133AXI
Description
CY7C0831AV-133AXI
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0831AV-133AXI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
2M (128K x 18)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Package / Case
120-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C0831AV-133AXI
Manufacturer:
CYPRESS
Quantity:
246
Part Number:
CY7C0831AV-133AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document #: 38-06059 Rev. *S
34. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS
35. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
36. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
37. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
38. CE
39. CE
= ADDRESS
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
ADDRESS
ADDRESS
0
DATA
DATA
0
= BE0 – BE1 = R/W = LOW; CE
= OE = BE0 – BE1 = LOW; CE
ADDRESS
DATA
OUT(B2)
OUT(B1)
CE
CE
DATA
CLK
(B2)
(B1)
(B1)
(B2)
(B2)
CLK
R/W
OUT
.
CE
IN
t
t
t
t
SA
SC
SA
SC
t
t
t
SW
SC
SA
A
A
A
0
0
n
t
CH2
t
1
CH2
1
(continued)
= R/W = CNTRST = MRST = HIGH.
Figure 11. Read-to-Write-to-Read (OE = LOW)
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, because OE = LOW, the Write operation cannot be
t
t
t
t
t
t
CYC2
CYC2
t
HA
HC
HA
HC
t
t
HW
HC
HA
t
t
CL2
CL2
A
A
READ
A
n+1
1
1
t
CD2
Figure 10. Bank Select Read
t
CD2
t
SW
t
SC
Q
n
Q
t
0
SC
A
n+2
A
t
A
CKHZ
NO OPERATION
2
2
t
t
DC
HC
t
HW
t
HC
t
CD2
t
SD
A
D
n+2
n+2
Q
t
[34, 35]
HD
A
A
1
3
t
3
t
DC
t
CKLZ
CKHZ
WRITE
t
[33, 36, 37, 38, 39]
CD2
CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
A
n+3
Q
A
A
4
2
4
t
t
t
CD2
CKHZ
CKLZ
READ
t
CKLZ
A
Q
n+4
3
t
CD2
A
A
5
t
5
CKLZ
t
t
CKHZ
CD2
Q
Page 17 of 28
n+3
Q
4
(B1)
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