CY7C0851V-167BBC Cypress Semiconductor Corp, CY7C0851V-167BBC Datasheet
CY7C0851V-167BBC
Specifications of CY7C0851V-167BBC
Available stocks
Related parts for CY7C0851V-167BBC
CY7C0851V-167BBC Summary of contents
Page 1
... A counter-mask register is used to control the counter wrap. The counter and mask register operations are described in more detail in the following sections. New features added to the CY7C0851V/CY7C0852V/ CY7C0831V/CY7C0832V devices include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, ...
Page 2
... Interrupt INT L Logic Note: 1. CY7C0851V has 16 address bits instead of 17. CY7C0832V has 18 address bits instead of 17. CY7C083XV does not have B2 and B3 inputs. CY7C083XV does not have DQ18–DQ35 data bits. JTAG not implemented on CY7C083XV. Document #: 38-06059 Rev. *I I/O I/O Control Control ...
Page 3
... CNTENL DQ26L L [2] A16L A14L DQ22L DQ18L M DQ24L DQ20L DQ8L DQ6L N DQ23L DQ21L TDO VSS P Note: 2. For CY7C0851V, pins M1 and M14 are NC. Document #: 38-06059 Rev. *I 172-ball BGA Top View DQ13L VDD DQ11L DQ11R VDD DQ14L DQ12L DQ9L DQ9R DQ12R INTL DQ15L ...
Page 4
... A 13L 40 A 14L 41 A 15L 42 A 16L 43 DQ 24L 44 DQ 20L Document #: 38-06059 Rev. *I 176-pin Thin Quad Flat Pack (TQFP) Top View CY7C0851V CY7C0852V CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V DQ 132 34R DQ 131 35R NC 130 A 129 0R A 128 1R A 127 2R A 126 3R V 125 ...
Page 5
... MAX Max. Access Time (Clock to Data) Typical Operating Current I CC Typical Standby Current for I SB3 (Both Ports CMOS Level) Notes for CY7C0831V. Document #: 38-06059 Rev. *I 120-pin Thin Quad Flat Pack (TQFP) Top View CY7C0831V CY7C0832V -167 167 4.0 200 55 CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V ...
Page 6
... JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Ground Inputs. Power Inputs. CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V Description . MAX is asserted LOW when ...
Page 7
... 1FFFE H = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the 1 CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V flag, a Write operation by the left port to R LOW. At least one byte has Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. ...
Page 8
... This section describes the CY7C0852V and CY7C0831V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0832V has 18 address bits, register lengths of 18 bits, and a maximum address value of 3FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF ...
Page 9
... When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0851V/CY7C0852V as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations ...
Page 10
... From Mask 17 From Counter Figure 1. Counter, Mask, and Mirror Logic Block Diagram Document #: 38-06059 Rev. *I Load/Increment 17 Mirror Increment Logic Wrap 17 Bit CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V Mask Register Counter/ Address Address Decode Register Counter To Readback 1 and Address 0 Decode 17 Wrap Wrap Detect 17 To Counter [1] RAM ...
Page 11
... Disabling the JTAG Feature It is possible to operate the CY7C0851V/CY7C0852V without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW ( prevent clocking of the device. TDI SS and TMS are internally pulled up and may be unconnected ...
Page 12
... IDCODE value for the CY7C0852V is 0C002069h. High-Z The High-Z instruction causes the bypass register to be connected between the TDI and TDO pins when the TAP controller Shift-DR state. It also places all CY7C0851V/ CY7C0852V outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When ...
Page 13
... JTAG TAP pins (TDI, TMS, TDO, TCK), MRST, and all power and ground pins have no scan cell. Other CY7C0851V/ CY7C0852V inputs have only the data scan cell. Active and Standby Supply Current ...
Page 14
... Instruction Field Revision Number (31:28) 0h [15] Cypress Device ID (27:12) C002h Cypress JEDEC ID (11:1) 034h ID Register Presence (0) 1 Note: 15. Cypress Device ID is C001h for Cypress part CY7C0851V. Document #: 38-06059 Rev. *I Bypass Register (BYR Instruction Register (IR Identification Register (IDR) n-1 Boundary Scan Register (BSR) ...
Page 15
... Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. ...
Page 16
... 125 C Operating Range Range Commercial + 0.5V DD Industrial Description MAX MAX – 0.2V MAX Description ° 3.3V DD CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V Ambient Temperature ° ° +70 C ° ° – +85 C -167 -133 Min. Typ. Max. Min. Typ. Max. 2.4 2.4 0.4 2.0 2.0 0.8 – ...
Page 17
... CNT/MSK Hold Time HCM t Output Enable to Data Valid OE [19, 20 Low Z OLZ Document #: 38-06059 Rev. *I OUTPUT V = 1.5V TH (b) Three-state Delay (Load 2) 3.0V 90% 10% Vss < Description CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3. 590 Ω 435 Ω 90% 10% < -167 -133 Min. Max. Min. Max. 167 133 6.0 7.5 2.7 3.0 2 ...
Page 18
... CY7C0851V/CY7C0852V -167/-133 Min. Max. 10 100 Page Unit ...
Page 19
... Test Data-In TDI Test Data-Out TDO Switching Waveforms Master Reset t RS MRST t ALL RSF ADDRESS/ DATA t LINES RSS ALL INACTIVE OTHER INPUTS TMS CNTINT INT TDO Document #: 38-06059 Rev TMSS t t TDIS t TDOX t RSR ACTIVE CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V TCYC TMSH t TDIH t TDOV Page ...
Page 20
... Numbers are for reference only. Document #: 38-06059 Rev CYC2 t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V IL CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V n n+1 t OHZ t OLZ t OE constantly loads the address on the rising edge of the CLK. IH Page ...
Page 21
... SA HA DATA IN DATA OUT Notes: 25. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data sheet. ADDRESS = ADDRESS . (B1) (B2) 26. ADS = CNTEN= B0 – LOW; MRST = CNTRST = CNT/MSK = HIGH. 27. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. ...
Page 22
... READ EXTERNAL ADDRESS Document #: 38-06059 Rev. *I [24, 27, 29, 30 n+1 n n+2 t CD2 OHZ READ WRITE [29] t SAD t SCN t CD2 READ WITH COUNTER CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V n+3 n+4 D n+3 READ t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER n+5 t CD2 Q n+4 Q n+3 Page ...
Page 23
... CL2 CLK ADDRESS n INTERNAL A ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D DATA WRITE EXTERNAL ADDRESS Document #: 38-06059 Rev. *I [30 n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V A A n+2 n n+2 n+3 WRITE WITH COUNTER A n+4 n+4 Page ...
Page 24
... COUNTER RESET Notes: 31 – LOW MRST = CNT/MSK = HIGH 32. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06059 Rev CD2 t CKLZ WRITE READ ADDRESS 0 ADDRESS 1 ADDRESS 0 CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V CD2 READ READ READ ADDRESS A ...
Page 25
... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06059 Rev. *I [33, 34, 35, 36 CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V n+4 n+2 n n+1 n+2 n+3 Page ...
Page 26
... R_Port will Read the most recent data (written by L_Port) (t CCS Document #: 38-06059 Rev. *I [37, 38, 39 CKLZ CCS CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V t CD2 violated, indeterminate data will be Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CYC2 CD2 Page ...
Page 27
... CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 43. The mask register assumed to have the value of 1FFFFh. 44. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06059 Rev. *I [40, 41, 42, 43, 44] 1FFFE 1FFFD 1FFFF t SCINT CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V Last_Loaded Last_Loaded +1 t RCINT Page ...
Page 28
... OE = LOW R/W = HIGH Document #: 38-06059 Rev n SINT 1FFFF m+1 m [1, 4, 50, 51, 52 CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V A A n+2 n+3 t RINT A m+3 Outputs – DQ Operation 0 35 High-Z Deselected High-Z Deselected D Write IN D Read OUT High-Z Outputs Disabled A m+4 Page ...
Page 29
... Speed (MHz) Ordering Code 167 CY7C0831V-167AC 133 CY7C0831V-133AC 64K × 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM Speed (MHz) Ordering Code 167 CY7C0851V-167BBC CY7C0851V-167AC 133 CY7C0851V-133BBC CY7C0851V-133AC CY7C0851V-133BBI Document #: 38-06059 Rev. *I Package Name Package Type A120 120-pin Flat Pack 14 mm × (TQFP) A120 120-pin Flat Pack 14 mm × ...
Page 30
... Package Diagrams 120-pin thin Quad Flatpack (14 × 14 × 1.4 mm) A120 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176 Document #: 38-06059 Rev. *I CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 51-85100-** 51-85132-** Page ...
Page 31
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 172-Ball FBGA ( 1.25 mm) BB172 CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 51-85114-*B ...
Page 32
... Document History Page Document Title: CY7C0851V/CY7C0852V/CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchro- nous Dual-Port RAM Document Number: 38-06059 Issue REV. ECN NO. Date ** 111473 11/27/01 *A 111942 12/21/01 *B 113741 04/02/02 *C 114704 04/24/02 *D 115336 07/01/02 *E 122307 12/27/02 *F 123636 1/27/03 *G 126053 08/11/03 *H 129443 11/03/03 ...