CY7C09579V-83BBC Cypress Semiconductor Corp, CY7C09579V-83BBC Datasheet
CY7C09579V-83BBC
Specifications of CY7C09579V-83BBC
Available stocks
Related parts for CY7C09579V-83BBC
CY7C09579V-83BBC Summary of contents
Page 1
... CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3 × 36 FLEx36 Synchronous Dual-Port Static RAM Features True dual-ported memory cells which allow simultaneous ■ access of the same memory location Two flow-through/pipelined devices ■ × 36 organization (CY7C09569V) ❐ × 36 organization (CY7C09579V) ❐ 0.25-micron CMOS for optimum speed/power ■ ...
Page 2
... K devices Document Number: 38-06054 Rev. *E Right Port Control Logic 9 9 I/O I/O Control Control 9 9 Counter/ True Dual-Ported Address RAM Array Register Decode CY7C09569V CY7C09579V R FT/Pipe R BE 9/18/36 Bus I/O R Match BM SIZE 14/15 [1] A –A 0 13/14R CLK R ADS ...
Page 3
... Document Number: 38-06054 Rev. *E Left Port Operation ......................................................... 24 Counter Operation .......................................................... 25 Bus Match Operation ..................................................... 25 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Sales, Solutions, and Legal Information ...................... 32 Worldwide Sales and Design Support ....................... 32 Products .................................................................... 32 PSoC Solutions ......................................................... 32 CY7C09569V CY7C09579V Page [+] Feedback ...
Page 4
... A12L 31 A13L 32 [ I/O26L 34 I/O25L 35 I/O24L 36 Notes 2. This pin is A14L for CY7C09579V. 3. This pin is A14R for CY7C09579V. Document Number: 38-06054 Rev. *E 144-pin Thin Quad Flatpack (TQFP) Top View CY7C09569V (16 K × 36) CY7C09579V (32 K × 36) CY7C09569V CY7C09579V 108 I/O33R I/O34R 107 106 I/O35R ...
Page 5
... L A13L FT/PIPEL CNTENL [ I/O22L I/O18L N I/O24L I/O20L I/O8L P I/O23L I/O21L NC Notes 4. This pin is A14L for CY7C09579V. 5. This pin is A14R for CY7C09579V. Document Number: 38-06054 Rev. *E 172-ball Ball Grid Array (BGA) Top View VSS I/O13L VDD I/O11L I/O11R VDD I/O13R VSS NC I/O15L I/O10L I/O10R I/O15R ...
Page 6
... BM, SIZE Select Pins for Bus Matching. See Bus Matching for details – BE Big Endian Pin. See Bus Matching for details V Ground Input SS V Power Input DD Document Number: 38-06054 Rev. *E Description –A for –A for 32 K devices CY7C09569V CY7C09579V MAX Page [+] Feedback ...
Page 7
... MAX Test Conditions MHz CY7C09569V CY7C09579V Ambient Temperature V DD 3.3 V 165 +70 C CY7C09569V CY7C09579V -100 -83 Typ Max Min Typ Max – – 2.4 – – – – 0.4 – – 0.4 – – 2.0 – – – ...
Page 8
... External AC Test Load Capacitance = 10 pF. 9. (Internal I/O pad Capacitance = 10 pF Test Load. Document Number: 38-06054 Rev. *E Output = 1 (b) Three-State Delay (Load 2) 3.0 V 90% 10 100 200 Capacitance (pF) (b) Load Derating Curve CY7C09569V CY7C09579V 3 590 435 90% 10% Page [+] Feedback ...
Page 9
... Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-Up Time CCS Notes 10. This parameter is guaranteed by design, but it is not production tested. 11. Test conditions used are Load 2. Document Number: 38-06054 Rev. *E CY7C09569V CY7C09579V CY7C09569V/CY7C09579V –100 –83 Min Max Min Max – 67 – 45 – ...
Page 10
... n+1 t OHZ [12, 13, 14, 15 CL2 n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ t OLZ t ...
Page 11
... Cycle Cycle [16, 17, 18, 19 CD2 CD2 t CLKZ 1st Cycle following the next rising edge of the clock. IH only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V A n n+1 n+1 1st 2nd Cycle Cycle n+1 t CD2 n 2nd Cycle 1st Cycle ...
Page 12
... CD2 SC CKHZ CKLZ [22, 23, 24, 25, 26] No Match t CD1 No Match t CWDD Valid , CNTRST = for the left port, which is being written to. IH CY7C09569V CY7C09579V CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 Valid >maximum specified, then data is not valid CWDD CCS Page [+] Feedback ...
Page 13
... During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 38-06054 Rev. *E [27, 28, 29, 30 n+1 n CD2 CKHZ Q n Read No Operation constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V A A n+3 n CD2 CKLZ Q n+3 Write Read Page [+] Feedback ...
Page 14
... IH 34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 38-06054 Rev. *E [31, 32, 33, 34 n+1 n+2 n n+2 n+3 t CD2 OHZ Write CY7C09569V CY7C09579V A A n+4 n CKLZ CD2 Q n+4 Read Page [+] Feedback ...
Page 15
... Word 2nd Word D D n+2 n Write Write Read Operation 2nd Cycle 1st Cycle 2nd Cycle only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V n+3 n+4 n+4 n+3 2nd Word 1st Word Q Q n+3 n+3 t CD2 t DC Read Read ...
Page 16
... CD1 Q n+1 t CKHZ No Read Operation [42 , 43, 46, 47, 48 n+1 n+2 n n+2 n OHZ Read Write constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V n+3 n CD1 CD1 Q n CKLZ DC Write Read A A n+4 n CD1 t CD1 Q n CKLZ ...
Page 17
... n+1 n+1 2nd Word 1st Word t CKHZ Q n 2nd Word No Write Write Operation 1st Cycle 2nd Cycle only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V n+1 n+2 n CD1 CD1 Q Q n+1 n CKLZ Read Read 1st Cycle 2nd Cycle ...
Page 18
... SAD HAD t t SCN HCN t CD2 n+1 Counter Hold Read with Counter [56] t SAD t SCN Q Q n+1 Counter Hold Read with Counter CY7C09569V CY7C09579V Q Q n+2 n+3 Read with Counter t HAD t HCN Q Q n+2 n+3 n Read DC DC with t t CD1 Counter ...
Page 19
... CNTRST = V IL 58. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V Document Number: 38-06054 Rev n n+1 n+1 n+2 Write with Write Counter Counter Hold . IH and CNTRST CY7C09569V CY7C09579V [57, 58 n+2 n+3 n n+3 n+4 Write with Counter . Page [+] Feedback ...
Page 20
... No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 63. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA during a valid WRITE cycle. Document Number: 38-06054 Rev. *E [59, 60, 61, 62, 63 CD2 Q t CKLZ Read Read Address 0 Address 1 CY7C09569V CY7C09579V ...
Page 21
... No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA during a valid WRITE cycle. Document Number: 38-06054 Rev. *E [64, 65, 66, 67, 68 CD1 Q 0 Write Read Address 0 Address 0 Address 1 CY7C09569V CY7C09579V n n Read Read ...
Page 22
... SCN HCN CA2 Read with t Counter DC [69, 70, 72] A n+1 t SAD n+1 Read with Counter is extended by 1 cycle. N CY7C09569V CY7C09579V A A n+2 n+1 HAD Q Q n+1 n+2 Counter Read With Counter Hold A A n+3 n+2 t HAD t t HCN SCN Q Q n+2 n+3 ...
Page 23
... R/W ADS CNTEN CNTRST CY7C09569V CY7C09579V Operation [76] Deselected Write [76] Read Outputs disabled Mode Operation Reset Counter reset Load Address load into counter Hold + External address blocked - Read counter address readout Hold External address blocked - counter disabled Increment Counter increment Page [+] Feedback ...
Page 24
... I/O Pins used on 1st Cycle I/O 3L–17L I/O 3R–17R I/O 2R–17R I/O 0R–8R I/O I/O I/O 18–26 I/O 27–35 CY7C09569V CY7C09579V I/O Pins used I/O 0R–35R I/O 0R–17R I/O 0R–8R Data on 3rd Cycle Data on 4th Cycle – – – – 18R–26R 27R– ...
Page 25
... For a x36 format (the only active format on the left port), each address counter in the CY7C09579V uses addresses (A For the right port (allowing for the bus-matching feature), a maximum of two address bits (out of a 2-bit sub-counter) are added ...
Page 26
... An internal sub-counter automatically increments the right port multiplexer control when Little or Big Endian operation is in effect. When transferring data in byte (9-bit) bus match format, the unused I/O pins (I/O ) are three-stated. 9RQ–35R CY7C09569V CY7C09579V Page [+] Feedback ...
Page 27
... CY7C09569V-100AXC CY7C09569V-100BBC 32K × 36 3.3 V Synchronous Dual-Port SRAM Speed Ordering Code (MHz) 100 CY7C09579V-100AC CY7C09579V-100AXC CY7C09579V-100BBC 83 CY7C09579V-83AC CY7C09579V-83AXC CY7C09579V-83BBC Ordering Code Definitions XXX X X Document Number: 38-06054 Rev. *E Package Package Type Name A144 144-pin Pb-free Thin Quad Flat Pack ...
Page 28
... Package Diagrams Document Number: 38-06054 Rev. *E Figure 3. 144-pin TQFP (20 × 20 × 1.4 mm) CY7C09569V CY7C09579V 51-85047 *C Page [+] Feedback ...
Page 29
... Document Number: 38-06054 Rev. *E Figure 4. 172-ball FBGA (15 × 15 × 1.25 mm) CY7C09569V CY7C09579V 51-85114 *C Page [+] Feedback ...
Page 30
... TQFP thin quad plastic flatpack TSOP thin small outline package WE write enable Document Number: 38-06054 Rev. *E Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V volts µA micro amperes mA milli amperes pF pico Farad °C degree Celsius W watts CY7C09569V CY7C09579V Page [+] Feedback ...
Page 31
... Document History Page Document Title: CY7C09569V/CY7C09579V 3 × 36 FLEx36 Document Number: 38-06054 Orig. of REV. ECN NO. Issue Date Change ** 110213 12/16/01 *A 122304 12/27/02 *B 349775 See ECN *C 2897215 03/22/10 RAME *D 3110406 12/14/2010 ADMU *E 3162642 02/04/2011 ADMU Document Number: 38-06054 Rev. *E ® Description of Change SZV ...
Page 32
... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06054 Rev. *E FLEx36 is a registered trademark of Cypress Semiconductor Corporation. All other products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised February 4, 2011 CY7C09569V CY7C09579V PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...