CY7C1315KV18-250BZC Cypress Semiconductor Corp, CY7C1315KV18-250BZC Datasheet - Page 11

• Manufacturer Part Number: CY7C1315KV18-250BZC
• Description: CY7C1315KV18-250BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315KV18-250BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Example
Figure 1
Truth Table
The truth table for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow.
Notes
Document Number: 001-58904 Rev. *C
Write cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
NOP: No operation
Standby: Clock stopped
2. X = ‘Don't Care’, H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected with the outputs in a tristate condition.
4. ‘A’ represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. ‘t’ represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ‘t’ clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. If this signal was LOW to initiate the previous cycle, this signal becomes a ‘Don’t Care’ for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
MASTER
symmetrically.
second read or write request.
ASIC)
(CPU
BUS
or
Operation
shows four QDR II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Source K#
Delayed K
Source K
DATA IN
Address
WPS#
BWS#
RPS#
Vt
R
R
Stopped
L–H
L–H
L–H
K
R = 50ohms
D
A
RPS WPS
H
L
H
X
[9]
[8]

represents rising edge.
R
P
L
S
#
Vt = Vddq/2
X
H
X
[9]
W
P
S
#
SRAM #1
Figure 1. Application Example
W
B
S
#
D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Q(A) at C(t + 1) Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)
D = X
Q = High Z
Previous state
C C#
DQ
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
D = X
Q = High Z
Previous state
DQ
CY7C1313KV18, CY7C1315KV18
CY7C1311KV18, CY7C1911KV18
D
A
R
D = X
Q = High Z
Previous state
Vt
Vt
R
P
#
S
W
P
S
#
DQ
[2, 3, 4, 5, 6, 7]
W
B
S
#
SRAM #4
C C#
CQ/CQ#
D = X
Q = High Z
Previous state
K
ZQ
K#
Q
Page 11 of 33
R = 250ohms
DQ
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