CY7C1360C-200BGC Cypress Semiconductor Corp, CY7C1360C-200BGC Datasheet - Page 16
![SRAM (Static RAM)](/photos/28/21/282110/119-bga_sml.jpg)
CY7C1360C-200BGC
Manufacturer Part Number
CY7C1360C-200BGC
Description
SRAM (Static RAM)
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1360C-200AJXC.pdf
(34 pages)
Specifications of CY7C1360C-200BGC
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
200MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
119-BGA
Density
9Mb
Access Time (max)
3ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
200MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
18b
Package Type
BGA
Operating Temp Range
0C to 70C
Number Of Ports
4
Supply Current
220mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
119
Word Size
36b
Number Of Words
256K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1360C-200BGC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1360C-200BGCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05540 Rev. *K
Notes
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
14. t
15. Test conditions are specified using the load in TAP AC test Conditions. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
[14, 15]
Description
R
/t
F
= 1 ns.
CY7C1360C, CY7C1362C
Min
50
20
20
–
–
0
5
5
5
5
5
5
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 16 of 34
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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