CY7C1361C-133AXIT Cypress Semiconductor Corp, CY7C1361C-133AXIT Datasheet - Page 26
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CY7C1361C-133AXIT
Manufacturer Part Number
CY7C1361C-133AXIT
Description
CY7C1361C-133AXIT
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1361C-133AJXC.pdf
(34 pages)
Specifications of CY7C1361C-133AXIT
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1361C-133AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Timing Diagrams
Notes
Document Number: 38-05541 Rev. *J
28. On this diagram, when CE is LOW: CE
29. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
30. GW is HIGH.
Data Out (Q)
Data In (D)
BWE, BW
ADDRESS
ADSC
ADSP
ADV
CLK
OE
CE
X
A1
High-Z
t ADS
Back-to-Back READs
t CES
t AS
Q(A1)
(continued)
A2
t ADH
t CEH
t
t AH
CH
t CYC
t
CL
1
Q(A2)
is LOW, CE
t
OEHZ
Figure 8. Read/Write Cycle Timing
A3
2
is HIGH and CE
Single WRITE
t
t DS
WES
D(A3)
t DH
t
WEH
3
is LOW. When CE is HIGH: CE
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
UNDEFINED
[28, 29, 30]
Q(A4+1)
BURST READ
1
is HIGH or CE
Q(A4+2)
CY7C1361C/CY7C1363C
2
is LOW or CE
Q(A4+3)
3
D(A5)
is HIGH.
Back-to-Back
A5
WRITEs
Page 26 of 34
D(A6)
A6
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