CY7C1470V33-167BZI Cypress Semiconductor Corp, CY7C1470V33-167BZI Datasheet
CY7C1470V33-167BZI
Specifications of CY7C1470V33-167BZI
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CY7C1470V33-167BZI Summary of contents
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... CY7C1474V33 available in Pb-free and non Pb-free 209-ball FBGA package IEEE 1149.1 JTAG boundary scan compatible n Burst capability—linear or interleaved burst order n “ZZ” sleep mode option and stop clock option n Logic Block Diagram – CY7C1470V33 (2 M × 36) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/LD ...
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... AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT E REGISTER 1 READ LOGIC Sleep Control CY7C1470V33 CY7C1472V33 CY7C1474V33 ...
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... PERFORMING A TAP RESET .................................. 13 TAP REGISTERS ...................................................... 13 TAP Instruction Set ................................................... 14 TAP Timing Diagram ...................................................... 15 TAP AC Switching Characteristics ............................... 15 3.3 V TAP AC Test Conditions ....................................... 16 2.5 V TAP AC Test Conditions ....................................... 16 Document Number: 38-05289 Rev. *M CY7C1470V33 CY7C1472V33 CY7C1474V33 TAP DC Electrical Characteristics And Operating Conditions ............................................. 16 Identification Register Definitions ................................ 17 Scan Register Sizes ....................................................... 17 Identification Codes ....................................................... 17 Boundary Scan Exit Order (2 M × ...
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... Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current Document Number: 38-05289 Rev. *M 250 MHz 200 MHz 3.0 3.0 500 500 120 120 CY7C1470V33 CY7C1472V33 CY7C1474V33 167 MHz Unit 3.4 ns 450 mA 120 mA Page [+] Feedback ...
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... DQb DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1470V33 CY7C1472V33 CY7C1474V33 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa CY7C1472V33 18 DQa 63 DQa DDQ DQa 59 DQa 58 NC ...
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... DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A Document Number: 38-05289 Rev. *M CY7C1470V33 ( 36 CEN CLK TDI A1 TDO TCK TMS CY7C1472V33 ( 18 CEN CLK ...
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... CEN DDQ DDQ DDQ MODE TDI CY7C1470V33 CY7C1472V33 CY7C1474V33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ V V DQf SS SS DQf V V DDQ DQf DQf DDQ NC ...
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... The direction of the pins is [17:0] –DQ are placed in a tristate condition. The outputs are automati controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1470V33 CY7C1472V33 CY7C1474V33 and DQP , BW controls DQ and DQP controls DQ and DQP , controls DQ and DQP . g ...
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... During normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Functional Overview The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are synchronous-pipelined burst NoBL SRAMs designed specifically to eliminate wait states during write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... CY7C1472V33) are automatically tristated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs ...
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... Truth Table The Truth Table for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows. Operation Address Used Deselect cycle None Continue deselect None cycle Read cycle (begin External burst) Read cycle (continue Next burst) NOP/dummy read External (begin burst) Dummy read (continue Next burst) Write cycle (begin ...
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... Partial Write Cycle Description The partial write cycle description for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows. Function (CY7C1470V33) Read Write – no bytes written Write byte a – (DQ and DQP ) a a Write byte b – (DQ and DQP ) b b Write bytes b, a Write byte c – (DQ and DQP ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470V33, CY7C1472V33, and CY7C1474V33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t plus CY7C1470V33 CY7C1472V33 CY7C1474V33 Page [+] Feedback ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOX DON’ UNDEFINED Description / ns CY7C1470V33 CY7C1472V33 CY7C1474V33 TDOV Min Max Unit 50 – ns – 20 MHz 20 – – ns – 10 ...
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... DDQ I = 100 µ 3 DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ GND < V < DDQ CY7C1470V33 CY7C1472V33 CY7C1474V33 to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 – V 2.0 – V 2.9 – V 2.1 – V – 0.4 V – 0.4 V – ...
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... Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. CY7C1470V33 CY7C1472V33 CY7C1474V33 Description ...
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... K11 60 165-ball ID Bit # P10 R10 37 25 R11 38 26 M10 39 CY7C1470V33 CY7C1472V33 CY7C1474V33 165-ball ID Bit # 165-ball ID J11 61 B7 K10 62 B6 J10 63 A6 H11 64 B5 G11 65 A5 F11 66 A4 E11 67 B4 D10 68 B3 D11 69 A3 C11 70 A2 G10 71 B2 F10 E10 A9 B9 A10 ...
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... J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1470V33 CY7C1472V33 CY7C1474V33 Bit # 209-ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 ...
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... DD ≤ V output disabled I DDQ, /2), undershoot: V (AC)> –2 V (Pulse width less than t CYC IL (Min) within 200 ms. During this time V < V and CY7C1470V33 CY7C1472V33 CY7C1474V33 Test Conditions Typ Max* Unit Logical 25 °C 361 394 single bit upsets Logical multi 25 °C 0 0.01 bit upsets Single event 85 ° ...
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... IN IL Test Conditions = 25 ° MHz 3 2.5 V DDQ 100 TQFP Test Conditions Package Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. CY7C1470V33 CY7C1472V33 CY7C1474V33 Min Max Unit – 500 mA – 500 mA – 450 mA – 245 mA – ...
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... R = 317 Ω 3 OUTPUT GND 351 Ω INCLUDING JIG AND (b) SCOPE R = 1667 Ω 2 DDQ OUTPUT GND 1538 Ω INCLUDING JIG AND (b) SCOPE CY7C1470V33 CY7C1472V33 CY7C1474V33 ALL INPUT PULSES DDQ 90% 90% 10% 10% ≤ ≤ (c) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) Page [+] Feedback ...
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... V minimum initially, before a read or write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same data EOLZ CHZ CLZ CY7C1470V33 CY7C1472V33 CY7C1474V33 –200 –167 Unit Min Max Min ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1470V33 CY7C1472V33 CY7C1474V33 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT ...
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... READ WRITE STALL NOP Q(A3) D(A4) DON’T CARE UNDEFINED [31, 32] Figure 9. ZZ Mode Timing High-Z DON’T CARE is LOW. When CE is HIGH HIGH LOW CY7C1470V33 CY7C1472V33 CY7C1474V33 CHZ D(A4) Q(A5) READ DESELECT CONTINUE Q(A5) DESELECT t ZZREC t RZZI DESELECT or READ Only is HIGH ...
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... Fine-Pitch Ball Grid Array ( 1.4mm) CY7C1474V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1470V33-167AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1472V33-167AXI CY7C1470V33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) 200 CY7C1470V33-200AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1472V33-200AXC CY7C1474V33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × ...
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... Package Diagrams Figure 10. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05289 Rev. *M CY7C1470V33 CY7C1472V33 CY7C1474V33 51-85050 *C Page [+] Feedback ...
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... Package Diagrams (continued) Figure 11. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 38-05289 Rev. *M CY7C1470V33 CY7C1472V33 CY7C1474V33 51-85165 *B Page [+] Feedback ...
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... Package Diagrams (continued) Figure 12. 209-ball FBGA ( 1.76 mm), 51-85167 Document Number: 38-05289 Rev. *M CY7C1470V33 CY7C1472V33 CY7C1474V33 51-85167 *A Page [+] Feedback ...
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... TDI test data input TMS test mode select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05289 Rev. *M CY7C1470V33 CY7C1472V33 CY7C1474V33 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes ...
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... Document History Page Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 Orig. of Submission Revision ECN Change ** 114676 PKS *A 121520 CJM *B 223721 NJY *C 235012 RYQ *D 243572 NJY *E 299511 SYT VBL *F 323039 ...
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... Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 Orig. of Submission Revision ECN Change *H 416221 RXU *I 472335 VKN *J 2756998 VKN *K 2903057 NJY 04/01/2010 *L 3033272 09/19/2010 *M 3052882 10/08/2010 Document Number: 38-05289 Rev. *M ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05289 Rev NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 8, 2010 CY7C1470V33 CY7C1472V33 CY7C1474V33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...