CY7C4285V-15ASXI Cypress Semiconductor Corp, CY7C4285V-15ASXI Datasheet - Page 8

• Manufacturer Part Number: CY7C4285V-15ASXI
• Description: CY7C4285V-15ASXI
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4285V-15ASXI

• Function: Synchronous
• Memory Size: 1.1K (64 x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 35mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2. Block Diagram of 8 K/16 K/32 K/64 K × 18 Low Voltage Synchronous FIFO Memory in Width Expansion Configuration
Depth Expansion Configuration (with Programmable Flags)
The CY7C4255/65/75/85V can easily be adapted to applications requiring more than 8 K/16 K/32 K/64 K words of buffering.
Figure 3 on page 9
Follow these steps:
Document Number: 38-06012 Rev. *D
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
FULL FLAG (FF)
DATA IN (D)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
shows Depth Expansion using three CY7C4255/65/75/85Vs. Maximum depth is limited only by signal loading.
LOAD (LD)
36
18
FF
RESET (RS)
7C4255V
7C4265V
7C4275V
7C4285V
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
EF
FIRST LOAD (FL)
18
18
FF
RESET (RS)
7C4255V
7C4265V
7C4275V
7C4285V
EF
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
18
DATA OUT (Q)
EMPTY FLAG (EF)
4275V–24
36
Page 8 of 24
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