CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet
CY7C67300-100AXA
Specifications of CY7C67300-100AXA
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CY7C67300-100AXA Summary of contents
Page 1
... Host Port Interface (HPI) with a DMA/Mailbox data path for an external processor to directly access all of the on-chip memory and control on-chip SIEs • Fast serial port supports from 9600 baud to 2.0 Mbaud CY7C67300 Block Diagram nRESET Control Watchdog Vbus, ID ...
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... Introduction EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low-cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high-perfor- mance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable I/O interface block allowing a wide range of interface options ...
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... Host and Peripheral ports simultaneously as shown in Port 1A Port 1B OTG – OTG – OTG – OTG – OTG – OTG – Host Host Any Combination of Ports Any Combination of Ports CY7C67300 UART I2C OTG UART I2C OTG Table 3. Port 2A Port 2B – – Host Host Host – – Host Peripheral – ...
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... Individually switchable internal pull up and pull down resistors on the USB Data Lines OTG Pins. 22 Table 5. OTG Interface Pins 23 Pin Name 18 DM1A 19 DP1A 9 OTGVBUS 10 OTGID 4 CSwitchA 5 CSwitchB CY7C67300 Port 2A Port 2B Peripheral – – Peripheral Host Host Host Host Peripheral – – Peripheral – Peripheral Peripheral – ...
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... Page 1 banking is always enabled and is in effect from 0x8000 to 0x9FFF. • Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF. • CPU memory bus strobes may wiggle when chip selects are inactive. CY7C67300 the address region of hardware (for ...
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... Interfacing to 64K x 8 External Memory Array EZ-Host CY7C67300 Document #: 38-08015 Rev. *G Table 6. External Memory Interface Pins (continued) Pin Name nBEL/A0 35 nBEH 36 D15 96 D14 95 D13 97 D12 38 D11 33 D10 External Memory Array A[15:0] A[15:0] D[7:0] D[7:0] nXRAMSEL CE nWR WE nRD OE CY7C67300 Pin Number 64K x 8 Page [+] Feedback ...
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... I C EEPROM Interface EZ-Host provides a master-only I serial EEPROMs. The serial EEPROM can be used to store application-specific code and data. This I be used for loading code out of EEPROM not a general interface. The I CY7C67300 Pin Number interface for external 2 C interface is only EEPROM interface is a BIOS implemen- ...
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... The HSS port has a few different pin location options as shown in Table 10. The port location is selectable via the GPIO Con- trol Register [0xC006]. Table 10.HSS Interface Pins Pin Name Default Location CTS RTS RXD TXD Alternate Location CTS RTS 61 RXD 60 TXD 66 CY7C67300 Pin Number Pin Number Page [+] Feedback ...
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... A1 A0 D15 D14 D13 D12 D11 44 D10 The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 13.HPI Addressing HPI A[1:0] HPI Data HPI Mailbox HPI Address HPI Status CY7C67300 [3, 4] Pin Number Table 13 ...
Page 10
... If the VBUS charge pump circuit is not to be used, 66 CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon- 86 nected. 87 Charge Pump Features 89 • Meets OTG Supplement Requirements, see DC Character- 90 istics: Charge Pump CY7C67300 Table 14 lists the Actual Max. Transfer Rate 3.2 MB/s 4.8 MB/s 7.38 MB/s 9.6 MB/s 12.0 MB VBUS C2 Table 54 for details ...
Page 11
... The booster circuit requires an external induc- tor, diode, and capacitor. During power down mode, the circuit is disabled to save power. The figure below shows how to con- nect the booster circuit 3.3V VCC C1 CY7C67300 2.7V to 3.6V power supply 3.0V to 3.6V power supply Page [+] Feedback ...
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... SPI mode, a serial interface with Mb/s transfer rate. At bootup GPIO[31:30] determine which of these three inter- faces are used for coprocessor mode. See Bootloading begins from the selected interface after POR + BIOS bootup. CY7C67300 Boot Mode 0 Host Port Interface (HPI) 1 High-Speed Serial (HSS) ...
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... Firmware should disable the charge pump (OTG Control Register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS only drops to V drops). • Booster circuit is turned off • USB transceivers is turned off • CPU goes into suspend mode until a programmable wakeup event. CY7C67300 p y Reset Logic 47Kohm 22pf 12MHz 22pf – ...
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... If more external memory is required, EZ-Host has enough address lines to support up to 512KB. However, this requires complex code banking/paging schemes via the Extended Page Registers. For further information on setting up the external memory, see the External Memory Interface Section. CY7C67300 and pin names Page [+] Feedback ...
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... Document #: 38-08015 Rev. *G Figure 10. Memory Map External Memory USER SPACE 0x4000- 0x7FFF 16K Extended Page 1 0x8000- 0x9FFF USER SPACE Banks Extended Page 2 0xA000- 0xBFFF USER SPACE Banks USER SPACE ~8K 0xC100- 0xDFFF CY7C67300 Bank Selected by 0xC018 Bank Selected by 0xC01A Page [+] Feedback ...
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... Carry for addition, or Borrow for subtraction. 1: Carry/Borrow occurred 0: Carry/Borrow did not occur Zero Flag (Bit 0) The Zero Flag bit indicates if an instruction execution resulted in a ‘0’. 1: Zero occurred 0: Zero did not occur CY7C67300 Address R/W 0xC000 R 0xC002 R/W 0xC004 ...
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... Document #: 38-08015 Rev. *G Figure 12. Bank Register Address... R/W R/W R Reserved R Hex Value 0x0100 0x000E << 0x001C 0x011C Figure 13. Revision Register Revision... ...Revision CY7C67300 R/W R/W R Binary Value 0000 0001 0000 0000 0000 0000 0001 1100 0000 0001 0001 1100 Page [+] Feedback ...
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... MHz/8 1000 48 MHz/9 1001 48 MHz/10 1010 48 MHz/11 1011 48 MHz/12 1100 48 MHz/13 1101 48 MHz/14 1110 48 MHz/15 1111 48 MHz/16 Reserved All reserved bits should be written as ‘0’. Document #: 38-08015 Rev. *G Figure 14. CPU Speed Register Reserved... - - - R CY7C67300 CPU Speed R/W R/W R Table 23. Page [+] Feedback ...
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... HPI interface read. 1: Enable wakeup on HPI interface read 0: Disable wakeup on HPI interface read GPI Wake Enable (Bit 4) The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition. 1: Enable wakeup on GPIO(25:24) transition 0: Disable wakeup on GPIO(25:24) transition CY7C67300 Reserved HSS SPI Wake ...
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... The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB Done, Host Wakeup/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1Endpoint n. 1: Enable Host 1 and Device 1 interrupt 0: Disable Host 1 and Device 1 interrupt CY7C67300 Reserved Host/Device 2 Host/Device 1 Interrupt Interrupt ...
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... Enable TM0 interrupt 0: Disable TM0 interrupt Reserved All reserved bits should be written as ‘0’. Figure 17. Breakpoint Register Address... R/W R/W R ...Address R/W R/W R Address (Bits [15:0]) The Address field is a 16-bit field containing the breakpoint address. CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
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... The Force Select field bit selects several different test condition states on the data lines (D+/D–). Refer to for details. Table 24.Force Select Definition Force Select [2:0] 1xx 01x 001 000 Reserved All reserved bits should be written as ‘0’. CY7C67300 Reserved... - - - ...
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... There are four registers dedicated to controlling the external memory interface. Each of these registers are covered in this section and are summarized in Table 26.External Memory Control Registers Register Name Extended Page 1 Map Register Extended Page 2 Map Register Upper Address Enable Register External Memory Control Register CY7C67300 Memory Arbitration Select W W ...
Page 24
... Upper Address Enable (Bit 3) The Upper Address Enable bit enables/disables the four most significant bits of the external address A[18:15]. 1: Enable A[18:15] of the external memory interface for general addressing. 0: Disable A[18:15], not available. Reserved All reserved bits should be written as ‘0’. CY7C67300 R/W R/W R/W 0 ...
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... All reserved bits should be written as ‘0’. Timer Registers There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized in Table Table 27.Timer Registers Register Name Watchdog Timer Register Timer 0 Register Timer 1 Register CY7C67300 XMEM Wait Select R/W R/W R ...
Page 26
... If this time The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoid a Watchdog trigger 1: Reset Count Reserved 1.4 ms All reserved bits should be written as ‘0’. 5.5 ms 22.0 ms 66.0 ms CY7C67300 R/W R/W R ...
Page 27
... Status Status Port A Force D± State State R/W R/W R Port B D+ Status (Bit 15) The Port B D+ Status bit is a read-only bit that indicates the value of DATA+ on Port HIGH LOW CY7C67300 R/W R/W R R/W R/W R UART Interface on page 7, and USB R/W R ...
Page 28
... In device mode this bit should be written as ‘0’. In host mode this bit enables or disables SOFs or EOPs for Port B. Either SOFs or EOPs will be generated depending on the LOB bit in the USB n Control Register when Port B is active. 1: Enable SOFs or EOPs 0: Disable SOFs or EOPs CY7C67300 Table 30 for Function Page [+] Feedback ...
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... Preamble Enable (Bit 7) The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should only be set when communicating with a low-speed device. 1: Enable Preamble packet 0: Disable Preamble packet CY7C67300 R/W R/W R/W R R/W R/W R/W ...
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... Endpoint disarmed Reserved All reserved bits should be written as ‘0’. Figure 27. Host n Address Register Address... R/W R/W R ...Address R/W R/W R Address (Bits [15:0]) The Address field sets the address pointer into internal RAM or ROM. CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 31
... Length Reserved Sequence Exception Status Flag the Host n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the Length Exception Flag set to ‘1’. 1: Overflow condition occurred 0: Overflow condition did not occur CY7C67300 Count... - R/W R R/W R/W R/W ...
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... For non-Isochronous transfers, the transaction was ACKed. For Isochronous transfers, the transaction was completed successfully 0: For non-Isochronous transfers, the transaction was not ACKed. For Isochronous transfers, the transaction did not complete successfully Figure 30. Host n PID Register Reserved - - - CY7C67300 Endpoint Select Page [+] Feedback ...
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... Register overflow condition occurs, Result [15:10] will be set to ‘111111’, a 2’s complement value indicating the additional byte count of the received packet underflow condition occurs, Result [15:0] indicates the excess bytes count (number of bytes not used). Reserved All reserved bits should be written as ‘0’. CY7C67300 ...
Page 34
... The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Enable ID interrupt 0: Disable ID interrupt CY7C67300 ...
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... Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Interrupt triggered 0: Interrupt did not trigger CY7C67300 SOF/EOP Reserved Interrupt Flag ...
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... R/W R/W R When this register is read, the value returned is the programmed SOF/EOP count value. Count (Bits [13:0]) The Count field sets the SOF/EOP counter duration. Reserved All reserved bits should be written as ‘0’. CY7C67300 Count... R/W R/W R R/W R/W ...
Page 37
... SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count Register (Host 1: 0xC092 Host 2: 0xC0B2). Frame (Bits [10:0]) The Frame field contains the next frame number to be transmitted. Reserved All reserved bits should be written as ‘0’. Document #: 38-08015 Rev Counter... ...Counter Figure 37. Host n Frame Register Reserved - - - ...Frame CY7C67300 Frame... Page [+] Feedback ...
Page 38
... IN and OUT requests. This bit should be set so that EP0 only excepts Setup packets at the start of each transfer. This bit must be cleared to except IN/OUT transactions. This bit only applies to EP0. 1: Ignore IN/OUT requests 0: Do not ignore IN/OUT requests CY7C67300 R/W R/W R/W R/W R/W ...
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... Do not allow transfers to an endpoint Arm Enable (Bit 0) The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete. 1: Arm endpoint 0: Endpoint disarmed Reserved All reserved bits should bit written as ‘0’. CY7C67300 Page [+] Feedback ...
Page 40
... The Count field sets the current transaction packet length for a single endpoint. Reserved All reserved bits should be written as ‘0’. Document #: 38-08015 Rev Address... R/W R/W R ...Address R/W R/W R Reserved - - - ...Count R/W R/W R CY7C67300 R/W R/W R R/W R/W R Count... - R/W R R/W R/W R Page [+] Feedback ...
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... Endpoint Count specified in the Device n Endpoint n Count Register. A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags (bits 11 and 10 respectively) should be checked to determine which event occurred overflow or underflow condition occurred 0: An overflow or underflow condition did not occur CY7C67300 Underflow OUT IN ...
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... Error occurred 0: Error did not occur ACK Flag (Bit 0) The ACK Flag bit indicates whether the last transaction was ACKed. 1: ACK occurred 0: ACK did not occur Result... R/W R/W R ...Result R/W R/W R CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 43
... EP4 Interrupt EP3 Interrupt Enable Enable Enable R/W R/W R VBUS Interrupt Enable (Bit 15) The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled, this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only CY7C67300 ...
Page 44
... Disable EP2 Transaction Done interrupt EP1 Interrupt Enable (Bit 1) The EP1 Interrupt Enable bit enables or disables endpoint one (EP1) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given Endpoint: CY7C67300 Page [+] Feedback ...
Page 45
... The Address field contains the USB address of the device assigned by the host. Reserved All reserved bits should be written as ‘0’. Figure 46. Device n Status Register Reserved - - - EP5 Interrupt EP4 Interrupt EP3 Interrupt Flag Flag Flag R/W R/W R CY7C67300 SOF/EOP Reset Interrupt Interrupt Flag Flag - R/W R/W X ...
Page 46
... EP1 Interrupt Flag (Bit 1) The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given EP: CY7C67300 Page [+] Feedback ...
Page 47
... Device n Interrupt Enable Register is set. Frame (Bits [10:0]) The Frame field contains the frame number from the last received SOF packet in full-speed mode. This field has no function for low-speed mode SOF Timeout occurs, this field contains the last received Frame number ...Count CY7C67300 Frame... Count... R ...
Page 48
... OTG D– dataline pull-up resistor enabled 0: OTG D– dataline pull-up resistor disabled D+ Pull-down Enable (Bit 7) The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line. 1: OTG D+ dataline pull-down resistor enabled 0: OTG D+ dataline pull-down resistor disabled CY7C67300 Table Address R/W C098H R/W 10 ...
Page 49
... Enable Write Protect 0: Disable Write Protect UD (Bit 14) The UD bit routes the Host/Device 1A Port’s transmitter enable status to GPIO[30]. This is for use with an external ESD protection circuit when needed. 1: Route the signal to GPIO[30 not route the signal to GPIO[30] CY7C67300 R/W R/W R/W R R/W R/W R ...
Page 50
... Interrupt 0 Enable (Bit 0) The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable Register must also be set in order for this for this interrupt to be enabled. 1: Enable IRQ0 0: Disable IRQ0 Reserved All reserved bits should be written as ‘0’. CY7C67300 Page [+] Feedback ...
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... Data... R/W R/W R 21/5 20/4 19/3 ...Data R/W R/W R Figure 52. GPIO n Input Data Register 29/13 28/12 27/11 Data... 21//5 20/4 19/3 ...Data CY7C67300 26/10 25/9 24/8 R/W R/W R 18/2 17/1 16/0 R/W R/W R 26/10 25/9 24 18/2 17/1 16 Page [+] Feedback ...
Page 52
... IDE Start Address Register IDE Stop Address Register IDE Control Register IDE PIO Port Registers Figure 54. IDE Mode Register Reserved... - - - ...Reserved - - R Table 40 for a definition of this field. CY7C67300 26/10 25/9 24/8 R/W R/W R 18/2 17/1 16/0 R/W R/W R Table 39. Address R/W 0xC048 R/W 0xC04A R/W ...
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... IDE PIO Mode 4 Reserved Reserved Disable IDE port operations Figure 55. IDE Start Address Register Address... R/W R/W R ...Address R/W R/W R Figure 56. IDE Stop Address Register Address... R/W R/W R ...Address R/W R/W R CY7C67300 R/W R/W R R/W R/W R R/W R/W R R/W R/W R Page [+] Feedback ...
Page 54
... Block transfer is complete 0: Clears IDE Done Flag IDE Enable (Bit 0) The IDE Enable bit will start a block transfer reset to ‘0’ when the block transfer is complete 1: Start block transfer 0: Block transfer complete Reserved All reserved bits should be written as ‘0’. CY7C67300 ...
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... Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. In the CY7C67300 register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits. The combination of IDE_nCS and IDE_A are the ATA interface register address ...
Page 56
... One Stop Bit (Bit 5) The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may vary and does not need to be fixed. 1: One stop bit 0: Two stop bits CY7C67300 CTS Receive ...
Page 57
... The Receive Ready Flag is a read-only bit that indicates if the HSS receive FIFO is empty or not. 1: HSS receive FIFO is not empty (one or more bytes is reading for reading) 0: HSS receive FIFO is empty Figure 59. HSS Baud Rate Register R/W R ...Baud R/W R/W R CY7C67300 Baud... R/W R/W R R/W R/W R Page [+] Feedback ...
Page 58
... The Data field contains the data received transmitted on the HSS port. Reserved All reserved bits should be written as ‘0’. Document #: 38-08015 Rev. *G Figure 60. HSS Transmit Gap Register Reserved - - - Transmit Gap Select R/W R/W R Figure 61. HSS Data Register Reserved - - - Data R/W R/W R CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 59
... All reserved bits should be written as ‘0’. Document #: 38-08015 Rev. *G Figure 62. HSS Receive Address Register Address... R/W R/W R ...Address R/W R/W R Figure 63. HSS Receive Counter Register Reserved - - - ...Counter R/W R/W R CY7C67300 R/W R/W R R/W R/W R Counter... - R/W R R/W R/W R Page [+] Feedback ...
Page 60
... All reserved bits should be written as ‘0’. Document #: 38-08015 Rev. *G Figure 64. HSS Transmit Address Register Address... R/W R/W R ...Address R/W R/W R Figure 65. HSS Transmit Counter Register Reserved - - - ...Counter R/W R/W R CY7C67300 R/W R/W R R/W R/W R Counter... - R/W R R/W R/W R Page [+] Feedback ...
Page 61
... SIE interrupt enable register. VBUS to HPI Enable (Bit 15) The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the onchip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port CY7C67300 Address R/W 0x0140 R 0x0142 R ...
Page 62
... When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. CY7C67300 Page [+] Feedback ...
Page 63
... TX Empty interrupt automatically clears when the CY7C67300 writes to this register. In addition, when the CY7C67300 writes to this register, the HPI_INTR signal on the HPI port asserts, signaling the external processor that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from this register ...
Page 64
... The SIE1msg Flag bit is a read only bit that indicates if the CY7C67300 CPU has written to the SIE1msg register. This bit is cleared on an HPI read. 1: The SIE1msg register has been written by the CY7C67300 CPU 0: The SIE1msg register has not been written by the ...
Page 65
... Figure 71. SPI Configuration Register SCK Polarity Scale Select Select R/W R/W R Enable R/W R/W R CY7C67300 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R Reserved R/W R Delay Select R/W R/W R Page ...
Page 66
... SS low to SCK active, SCK inactive to SS high, SS high time. 8 MHz This field only applies to master mode. 6 MHz 4 MHz 3 MHz 2 MHz 1.5 MHz 1 MHz 750 KHz 500 KHz 375 KHz 250 KHz 375 KHz 250 KHz 375 KHz 250 KHz CY7C67300 Page [+] Feedback ...
Page 67
... The Transmit Bit Length field controls whether a full byte or partial byte transmitted. If Transmit Bit Length is ‘000’ then a full byte will be transmitted. If Transmit Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be transmitted. CY7C67300 Read ...
Page 68
... FIFO underflow has occurred. Similarly, when set with the Receive Full bit of the SPI Control Register FIFO overflow has occured.This bit automatically clears when the SPI FIFO Init Enable bit of the SPI Control register is set. 1: Indicates FIFO error 0: Indicates no FIFO error CY7C67300 ...
Page 69
... Clear the block mode interrupt 0: No function Reserved All reserved bits should be written as ‘0’. Figure 76. SPI CRC Control Register CRC CRC Receive Enable Clear CRC R/W R/W R ...Reserved - - - Table 46. CY7C67300 Transmit Transfer Interrupt Interrupt Clear Clear - One in Zero in Reserved... CRC ...
Page 70
... The Zero in CRC bit is a read-only bit that indicates if the CRC value is all ones or not 1: CRC value is not all ones 0: CRC value is all ones Reserved All reserved bits should be written as ‘0’. Figure 77. SPI CRC Value Register CRC... R/W R/W R ...CRC R/W R/W R CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 71
... The Address field sets the base address for the SPI transmit DMA. Document #: 38-08015 Rev. *G Figure 78. SPI Data Register Reserved - - - Data R/W R/W R Figure 79. SPI Transmit Address Register Address... R/W R/W R ...Address R/W R/W R CY7C67300 R/W R/W R R/W R/W R R/W R/W R Page [+] Feedback ...
Page 72
... R/W R/W R Figure 81. SPI Receive Address Register Address... R/W R/W R ...Address R/W R/W R Figure 82. SPI Receive Count Register Reserved - - - ...Count R/W R/W R CY7C67300 Count... R/W R/W R R/W R/W R R/W R/W R R/W R/W R Count... R/W R/W R R/W R/W R Page [+] Feedback ...
Page 73
... UART Enable (Bit 0) The UART Enable bit enables or disables the UART. 1: Enable UART 0: Disable UART. This allows GPIO28 and GPIO27 to be used for general use. Reserved All reserved bits should bit written as ‘0’. CY7C67300 Address R/W 0xC0E0 R/W 0xC0E2 R 0xC0E4 ...
Page 74
... Transmit buffer is empty and ready for a new byte of data Figure 85. UART Data Register Reserved - - - Data R/W R/W R Data (Bits [7:0]) The Data field is where the UART data to be transmitted or received is located. Reserved All reserved bits should be written as ‘0’. CY7C67300 Receive Full Transmit Full - ...
Page 75
... PWM 3 Polarity Polarity Enable Select Select R/W R/W R Table 50.Prescaler Select Definition Prescale Select [11:9] 000 001 010 011 100 101 110 111 CY7C67300 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Prescale Mode Select Select R/W R/W ...
Page 76
... The PWM 0 Enable bit enables or disables PWM 0. 1: Enable PWM 0 0: Disable PWM 0 Figure 87. PWM Maximum Count Register Reserved - - - ...Count R/W R/W R Count (Bits [9:0]) The Count field sets the maximum cycle time. Reserved All reserved bits should be written as ‘0’. CY7C67300 Count... - R/W R R/W R/W R Page [+] Feedback ...
Page 77
... If the PWM Stop value is greater then the PWM Maximum Count value then the output stays at true. Reserved All reserved bits should bit written as ‘0’. Document #: 38-08015 Rev. *G Figure 88. PWM n Start Register Reserved - - - ...Address R/W R/W R Figure 89. PWM n Stop Register Reserved - - - ...Address R/W R/W R CY7C67300 Address... - R/W R R/W R/W R Address... - R/W R R/W R/W R Page [+] Feedback ...
Page 78
... The Count field designates the number of cycles (plus one) to run when in one shot mode. For example, Cycles = PWM Cycle Count + 1, therefore for 2 cycles set PWM Cycle Count = 1. Document #: 38-08015 Rev. *G Figure 90. PWM Cycle Count Register Count... R/W R/W R ...Count R/W R/W R CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 79
... CTS: HSS CTS I/O D14: External Memory Data Bus RTS: HSS RTS I/O D13: External Memory Data Bus RXD: HSS RXD (Data is received on this pin) I/O D12: External Memory Data Bus TXD: HSS TXD (Data is transmitted from this pin) CY7C67300 GND D8/MISO 74 D9/nSSI ...
Page 80
... MHz is required for normal operation so the CLKSEL pin must have a 47-kohm pull After reset this pin will function as A15. I/O GPIO31: General Purpose I/O SCK: I2C EEPROM SCK I/O GPIO30: General Purpose I/O SDA: I2C EEPROM SDA CY7C67300 CC. Page [+] Feedback ...
Page 81
... D15: D15 for HPI or IDE nSSI: SPI nSSI I/O GPIO14: General Purpose I/O D14: D14 for HPI or IDE I/O GPIO13: General Purpose I/O D13: D13 for HPI or IDE I/O GPIO12: General Purpose I/O D12: D12 for HPI or IDE CY7C67300 = 3.0V, CC Page [+] Feedback ...
Page 82
... Booster Power input: 2.7V to 3.6V Analog Booster switching output Output Ground Booster Ground Analog I/O USB OTG Vbus Analog Charge Pump Capacitor Analog Charge Pump Capacitor Power USB Power Ground USB Ground Power Main V CC Ground Main Ground CY7C67300 Description Page [+] Feedback ...
Page 83
... All tests were conducted with Charge pump off. Document #: 38-08015 Rev. *G Min. Typical 12 –500 20 Conditions 0< V < OUT I = –4 mA OUT to provide a nominal 3.3V V supply CY7C67300 + 0.5V CC Max. Unit MHz +500 PPM 33 pF 500 µ Min. Typ. Max. Unit 3.0 3.3 3 ...
Page 84
... LOAD LOAD LOAD LOAD 0V< V < 5.25V BUS mA 3.3V LOAD not being driven BUS Pull-up voltage = 3.0V values when only two transceivers are powered. CY7C67300 Min. Typ. Max. Unit 250 mV 80 100 mA 135 180 mA µA 210 500 µ µA 190 500 µ ...
Page 85
... Clock is 12-MHz nominal. v 12. XINH is required obtain an internal 50/50 duty cycle clock. Document #: 38-08015 Rev RESET t IOACT Reset Timing Min. 16 200 t LOW t FALL Clock Timing Min. 1.5 83. CY7C67300 Typical Max. Unit [11] clocks µs t RISE Typical Max. Unit 12.0 MHz 3.0 3.6 V 83.33 83 ...
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... External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = – 1)*T for wait states = n, n > 48-MHz AC clock period. 15. Read timing is applicable for nXMEMSEL, nXRAMSEL, and nXROMSEL. Document #: 38-08015 Rev RPW t AC Data Valid Min. Typical CY7C67300 t CDH t RDH Max. Unit Page [+] Feedback ...
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... The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18 – 1)*T for wait states = n, n > 48-MHz clock period. WPW 17. Write timing is applicable for nXMEMSEL, nXRAMSEL and nXROMSEL. Document #: 38-08015 Rev CSW t WPW t DW Data Valid Min 4.5 13 CY7C67300 Typical Max. Unit Page [+] Feedback ...
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... Input Fall Time F t Stop Setup Time SU.STO t Data Out Hold Time DH Document #: 38-08015 Rev HIGH LOW SU.DAT t HD.DAT t DH Min. Typical 1300 600 900 1300 600 600 0 100 600 0 CY7C67300 BUF t SU.STO Max. Unit 400 kHz 300 ns 300 Page [+] Feedback ...
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... Data Setup DSU t Write Data Hold WDH t Write Pulse Width WP t Write Cycle Time CYC Notes 18 system clock period = 1/48 MHz. Document #: 38-08015 Rev CYC CSH t t DSU WDH Min. Typical –1 –1 –1 – CY7C67300 Max. Unit [18] T [18] T Page [+] Feedback ...
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... Read Data Hold, relative to the earlier of RDH HPI_nRD rising or HPI_nCS rising t Read Pulse Width RP t Read Cycle Time CYC Document #: 38-08015 Rev CYC CSH t RDH t t ACC RDH Min. Typical –1 –1 –1 –1 1 CY7C67300 Max. Unit [18 [18] T [18] T Page [+] Feedback ...
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... STOP bit. (BT = bit period GAP bit 1 bit 2 bit 3 bit 4 bit +/- 5% CY7C67300 CPU may start another BYTE transmit right after TxRdy goes high bit 4 bit 5 bit 6 bit 7 stop bit start bit start of last data bit to TxRdy high: programmable 0 min max ...
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... Host/Device Host/Device Host/Device OTG 2A Wake 1B Wake 1A Wake Wake Enable Enable Enable Enable Reserved GPI Reserved Wake Enable CY7C67300 tCTShold Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low 0000 0000 0000 0000 SOF/EOP1 to Reset2 to HPI HPI Swap 1 0001 0100 CPU Enable ...
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... XOFF XOFF Polarity Polarity Enable Select Select Receive Done One Transmit Packet Mode Interrupt Flag Stop Bit Ready Select HSS Baud... CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low 0000 0000 Lock WDT Reset 0000 0000 Enable Enable ...
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... Interrupt Count Counter... Count... Port A Port B Connect Port A Con- Reserved Wake Interrupt Change nect Change Enable Interrupt Interrupt Enable Enable CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low Counter... 0000 0000 0000 0000 0000 0000 Arm 0000 0000 ...
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... Enable Clear CRC Scale Select Baud Select Reserved Prescale Select PWM2 PWM1 PWM0 PWM3 Polarity Select Polarity Select Polarity Select Enable CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low Wake SOF/EOP Reset 0000 0000 Interrupt Interrupt Interrupt Enable ...
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... Document #: 38-08015 Rev. *G Bit 14 Bit 13 Bit 12 Bit 11 Bit 6 Bit 5 Bit 4 Bit 3 ID Reserved SOF/EOP2 Reserved Flag Flag SIE1msg Done2 Flag CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low Address... 0000 0000 0000 0000 0000 0000 0000 0000 SOF/EOP1 Reset2 Mailbox In ...
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... TYP. DETAIL 51 50 12°±1° (8X) TOP LEFT CORNER CHAMFER 1.40±0.05 A SEE DETAIL 2 C system, provided that the system conforms to the I CY7C67300 Temperature Range X –40 to 85°C X –40 to 85°C X –40 to 85°C X –40 to 85°C R 0.08 MIN. 0° MIN. ...
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... Document History Page Document Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host/Peripheral Controller with Automotive AEC Grade Support Document Number: 38-08015 REV. ECN NO. Issue Date Change ** 111872 03/22/02 *A 116989 08/23/02 *B 125262 04/10/03 *C 126210 05/23/03 *D 127335 05/29/03 *E 129395 10/01/03 *F 443992 See ECN ...