CY7C68001-56LFXC Cypress Semiconductor Corp, CY7C68001-56LFXC Datasheet - Page 21

• Manufacturer Part Number: CY7C68001-56LFXC
• Description: IC,Bus Controller,LLCC,56PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1942; CY7C68001-56LFXC

Following is the bit definition for the same register when the
device is operating at full speed and the endpoint is not
configured as isochronous endpoint.
9.7.1 DECIS: EPxPFH.7
If DECIS = 0, then PF goes high when the byte count i is equal
to or less than what is defined in the PF registers. If DECIS = 1
(default), then PF goes high when the byte count equal to or
greater than what is set in the PF register. For OUT endpoints,
the byte count is the total number of bytes in the FIFO that are
available to the external master. For IN endpoints, the byte count
is determined by the PKSTAT bit.
9.7.2 PKSTAT: EPxPFH.6
For IN endpoints, the PF can apply to either the entire FIFO,
comprising multiple packets, or only to the current packet being
filled. If PKTSTAT = 0 (default), the PF refers to the entire IN
endpoint FIFO. If PKTSTAT = 1, the PF refers to the number of
bytes in the current packet.
Document #: 38-08013 Rev. *J
Full Speed Non-ISO Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
Full Speed Non-ISO Mode:
EP2PFH, EP6PFH
Full Speed Non-ISO Mode:
EP4PFH, EP8PFH
PKTSTAT
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
Bit #
Bit Name
Read/Write
Default
0
1
PKTS[1]
DECIS PKTSTAT OUT:
Number of committed packets
+ current packet bytes
Current packet bytes only
PFC7
OUT:
R/W
R/W
DECIS
IN:
R/W
7
0
7
1
7
0
PKTS[0]
PFC6
OUT:
PF applies to
R/W
R/W
IN:
6
0
STAT
PKT-
6
0
R/W
6
0
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
R/W
PFC12
5
0
R/W
R/W
5
0
5
0
0
R/W
PFC11
OUT:
4
0
R/W
PFC10
OUT:
4
0
R/W
4
0
R/W
PFC10
OUT:
R/W
3
0
PFC9
3
1
OUT:
R/W
EPnPFH:L format
PKTS[] and PFC[]
3
1
R/W
R/W R/W
2
0
2
0
0
R/W R/W
2
0
0
PFC[ ]
PFC9
R/W
1
0
1
0
0x13, 0x15,
0x17, 0x19
0x12, 0x16
0
1
0x14, 0x18
0
PKTS[2]
PFC8
OUT:
R/W
R/W
IN:
PFC8
R/W
0
0
0
0
0
0
9.7.3 IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3]
These three bits have a different meaning, depending on
whether this is an IN or OUT endpoint.
IN Endpoints
If IN endpoint, the meaning of this EPxPFH[5:3] bits depend on
the PKTSTAT bit setting. When PKTSTAT = 0 (default), the PF
considers when there are PKTS packets plus PFC bytes in the
FIFO. PKTS[2:0] determines how many packets are considered,
according to
Table 9-5. PKTS Bits
When PKTSTAT = 1, the PF considers when there are PFC bytes
in the FIFO, no matter how many packets are in the FIFO. The
PKTS[2:0] bits are ignored.
OUT Endpoints
The PF considers when there are PFC bytes in the FIFO
regardless of the PKTSTAT bit setting.
9.8 EPxISOINPKTS Registers 0x1A–0x1D
For ISOCHRONOUS IN endpoints only, these registers
determine the number of packets per frame (only one per frame
for full speed mode) or microframe (up to three per microframe
for high speed mode), according to the following table.
Table 9-6. EPxISOINPKTS
Bit #
Bit Name
Read/Write
Default
PKTS2
EP2ISOINOKTS, EP4ISOINPKTS,
EP6ISOINPKTS, EP8ISOINPKTS
0
0
0
0
1
INPPF1
0
0
1
1
Table
R/W
7
0
0
PKTS1
0
0
1
1
0
R/W
9-5.
6
0
0
R/W
INPPF0
5
0
0
PKTS0
0
1
0
1
R/W
4
0
0
0
1
0
1
0
R/W
3
0
0
Number of Packets
INPPF2 INPPF1 INPPF0
R/W
2
0
CY7C68001
1 (default)
Packets
Invalid
0
1
2
3
4
R/W
2
3
Page 21 of 45
1
0
0x1A, 0x1B,
0x1C, 0x1D
R/W
0
1
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