CY7C68013A-56LTXCT Cypress Semiconductor Corp, CY7C68013A-56LTXCT Datasheet - Page 25

• Manufacturer Part Number: CY7C68013A-56LTXCT
• Description: CY7C68013A-56LTXCT
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LTXCT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Processor Series: CY7C68xx
• Core: 8051
• Development Tools By Supplier: CY3684
• Package: 56QFN EP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 24
• Interface Type: I2C/USART/USB
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Details

Table 11. FX2LP Pin Descriptions (continued)
Document #: 38-08032 Rev. *M
TQFP
Port E
128
104
105
121
122
123
124
108
109
110
111
TQFP
100
82
83
95
96
97
98
86
87
88
89
SSOP
56
54
55
56
1
2
3
QFN
56
47
48
49
50
51
52
56 VF-
BGA
6B
6A
3B
3A
3C
2A
PD2 or
FD[10]
PD3 or
FD[11]
PD4 or
FD[12]
PD5 or
FD[13]
PD6 or
FD[14]
PD7 or
FD[15]
PE0 or
T0OUT
PE1 or
T1OUT
PE2 or
T2OUT
PE3 or
RXD0OUT
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
(PD2)
(PD3)
(PD4)
(PD5)
(PD6)
(PD7)
(PE0)
(PE1)
(PE2)
(PE3)
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051
Timer-counter0. T0OUT outputs a high level for one
CLKOUT clock cycle when Timer0 overflows. If Timer0
is operated in Mode 3 (two separate timer/counters),
T0OUT is active when the low byte timer/counter
overflows.
Multiplexed pin whose function is selected by the
PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051
Timer-counter1. T1OUT outputs a high level for one
CLKOUT clock cycle when Timer1 overflows. If Timer1
is operated in Mode 3 (two separate timer/counters),
T1OUT is active when the low byte timer/counter
overflows.
Multiplexed pin whose function is selected by the
PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051
Timer2. T2OUT is active (HIGH) for one clock cycle
when Timer/Counter 2 overflows.
Multiplexed pin whose function is selected by the
PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0.
If RXD0OUT is selected and UART0 is in Mode 0, this
pin provides the output data for UART0 only when it is
in sync mode. Otherwise it is a 1.
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Description
Page 25 of 62
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