CY7C68013A-56PVXCT Cypress Semiconductor Corp, CY7C68013A-56PVXCT Datasheet - Page 48

• Manufacturer Part Number: CY7C68013A-56PVXCT
• Description: CY7C68013A-56PVXCT
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56PVXCT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Details
• Other names: CY7C68013A56PVXCT

10.13 Slave FIFO Output Enable
Table 29. Slave FIFO Output Enable Parameters
10.14 Slave FIFO Address to Flags/Data
Table 30. Slave FIFO Address to Flags/Data Parameters
Document #: 38-08032 Rev. *M
t
t
t
t
OEon
OEoff
XFLG
XFD
Parameter
Parameter
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
FIFOADR [1.0]
Figure 26. Slave FIFO Address to Flags/Data Timing Diagram
DATA
Figure 25. Slave FIFO Output Enable Timing Diagram
SLOE
FLAGS
DATA
Description
Description
t
OEon
t
XFLG
t
XFD
N
N+1
t
OEoff
Min
Min
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[20]
[20]
Max
10.5
10.5
Max
10.7
14.3
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Unit
Unit
ns
ns
ns
ns
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