CY8C3665AXI-016 Cypress Semiconductor Corp, CY8C3665AXI-016 Datasheet - Page 105

CY8C3665AXI-016

CY8C3665AXI-016

Manufacturer Part Number
CY8C3665AXI-016
Description
CY8C3665AXI-016
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C36xxr
Datasheets

Specifications of CY8C3665AXI-016

Core Processor
8051
Core Size
8-Bit
Speed
67MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Peripherals
CapSense, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
CY8C36
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
1KB
Ram Memory Size
4KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C3665AXI-016
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY8C3665AXI-016T
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Table 11-64. Synchronous Read Cycle Specifications
Document Number: 001-53413 Rev. *L
T
Tcp/2
Tceld
Tcehd
Taddrv
Taddriv
Toeld
Toehd
Tds
Tadscld
Tadschd
Parameter
Note
53. Limited by GPIO output frequency, see
EMIF clock period
EM_Clock pulse high
EM_CEn low to EM_Clock high
EM_Clock high to EM_CEn high
EM_Addr valid to EM_Clock high
EM_Clock high to EM_Addr invalid
EM_OEn low to EM_Clock high
EM_Clock high to EM_OEn high
Data valid before EM_OEn high
EM_ADSCn low to EM_Clock high
EM_Clock high to EM_ADSCn high
EM_ ADSCn
EM_ Addr
EM_ CEn
EM_ OEn
EM_ Clock
EM_ Data
Description
[53]
Table 11-10
Figure 11-64. Synchronous Read Cycle Timing
Tceld
Taddrv
Toeld
Tadscld
on page 74.
Vdda ≥ 3.3 V
Tcp/2
Tadschd
Tds
Conditions
Tcehd
Toehd
Data
Address
Taddriv
PSoC
T/2 – 5
T/2 – 5
T/2 – 5
T + 15
30.3
Min
T/2
5
5
5
T
5
®
3: CY8C36 Family
Typ
Data Sheet
Max
Page 105 of 126
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS

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