CY8C3866LTI-067 Cypress Semiconductor Corp, CY8C3866LTI-067 Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CY8C3866LTI-067
Manufacturer Part Number
CY8C3866LTI-067
Description
CY8C3866LTI-067
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C38xxr
Specifications of CY8C3866LTI-067
Core Processor
8051
Core Size
8-Bit
Speed
67MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Peripherals
CapSense, DMA, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x20b, D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C3866LTI-067
Manufacturer:
Cypress
Quantity:
260
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3
Low resistance output pin for high current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out
High current output of uncommitted opamp
Extref0, Extref1
External reference input to the analog system.
OpAmp0–, OpAmp1–, OpAmp2–, OpAmp3–
Inverting input to uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+
Noninverting input to uncommitted opamp.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense
I2C0: SCL, I2C1: SCL
I
Any I/O pin can be used for I
required.
I2C0: SDA, I2C1: SDA
I
Any I/O pin can be used for I
required.
Ind
Inductor connection to boost pump.
Document Number: 001-11729 Rev. *R
Note
2
2
12. GPIOs with opamp outputs are not recommended for use with CapSense.
C SCL line providing wake from sleep on an address match.
C SDA line providing wake from sleep on an address match.
[12]
.
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
2
2
C SCL if wake from sleep is not
C SDA if wake from sleep is not
Plane
Vssd
[12]
Vddd
.
Vssd
Vssa
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25-MHz crystal oscillator pin.
nTRST
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
SIO
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK
Serial wire debug clock programming and debug port
connection.
SWDIO
Serial wire debug input and output programming and debug port
connection.
SWV.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
Vdda
Plane
Vssa
PSoC
®
3: CY8C38 Family
Data Sheet
Page 10 of 129
[+] Feedback