CY8CTMG200-32LQXIT Cypress Semiconductor Corp, CY8CTMG200-32LQXIT Datasheet - Page 133

• Manufacturer Part Number: CY8CTMG200-32LQXIT
• Description: CY8CTMG200-32LQXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4.6
In compatibility mode, the SCL, as usual, is pulled low until the CPU responds by setting the Transmit/Receive bit and for
loading a byte in the I2C_DATA register (in case of transmit operation) even though IMO is operational.
trates the process of switching from direct clocking to sampled mode.
See the following notes regarding
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
a. After, the address matches IRQ and a signal called switch_to_sample_mode are asserted asynchronously.
b. This IRQ goes as input to the sleep controller block. The sleep controller block wakes the system by clearing the sleep
c. After IMO is operational, the signal switch_to_sample_mode is registered and asserted high, indicating IMO is opera-
d. The state machines and other logic are put at appropriate states when switching to sample mode.
switch_to_sample_mode
rel_switch_sample_mode
bit.
tional. When this registered signal becomes high, the switch_to_sample_mode signal deasserts asynchronously.
SCL
IMO
SDA
IRQ
Compatibility Mode Configuration
Figure
Figure 15-13. Direct Clocking to Sample Mode Timing
15-13:.
released once CPU is operational and responds by setting the
transmit/receive bit. It thenloads the I2C_DATA register with a
SCL is released here if buffer mode is enabled, otherwise it is
byte if it is a transmit operation
Figure 15-13
I2C Slave
illus-
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