CY8CTST200-24LQXIT Cypress Semiconductor Corp, CY8CTST200-24LQXIT Datasheet - Page 73
CY8CTST200-24LQXIT
Manufacturer Part Number
CY8CTST200-24LQXIT
Description
CY8CTST200-24LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-24LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
20
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-WQFN Exposed Pad, 24-HWQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep
and Watchdog registers, refer to the
isters in address order, refer to the
10.1
Device components that are involved in Sleep and Watchdog operation are the selected 32 kHz clock, the wakeup timer, the
Sleep bit in the CPU_SCR0 register, the sleep circuit (to sequence going into and coming out of sleep), the bandgap refresh
circuit (to periodically refresh the reference voltage during sleep), and the watchdog timer.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
10. Sleep and Watchdog
Architectural Description
32 kHz CLK
CPU_SCR0
OSC_SCR0
Sleep Timer
(SLP_CFG, SLP_CFG2,
Configuration Registers)
Register Decode Logic
SLP_CFG3, Internal
Register Reference chapter on page
IMO
CLK
Summary Table of the Core Registers on page
Figure 10-1. Sleep Controller Architecture
Wakeup Timer
CPU Hold
Off
187.
Sleep Control Logic
Control Inputs
24. For a quick reference of all PSoC reg-
Outputs
[+] Feedback
73
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