CY8CTST200A-16LGXI Cypress Semiconductor Corp, CY8CTST200A-16LGXI Datasheet - Page 131
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CY8CTST200A-16LGXI
Manufacturer Part Number
CY8CTST200A-16LGXI
Description
CY8CTST200A-16LGXI
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-16LGXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
13
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Synchronized)
15.4.3
Figure 15-8
which occurs on the positive edge of the ninth clock (byte +
ACK/NACK) in transmit mode and on the positive edge of
the eighth clock in receive mode. There is a maximum of
three cycles of latency due to the input synchronizer/filter
circuit. As shown, the interrupt occurs on the clock following
a valid SCL positive edge input transition (after the synchro-
nizers). The Address bit is set with the same timing but only
after a slave address has been received. The LRB (Last
Received Bit) status is also set with the same timing but only
on the ninth bit after a transmitted byte.
Figure 15-8. Byte Complete, Address, LRB Timing
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CLOCK
SCL_IN
SCL
IRQ
illustrates the interrupt timing for byte complete,
Transmit: Ninth positive edge SCL
Receive: Eighth positive edge SCL
Status Timing
and INTERRUPT
and INTERRUPT
START DETECT
Misplaced Start
Misplaced Stop
STOP DETECT
(Synchronized)
(Synchronized)
BUS ERROR
BUS ERROR
3 Cycles
Latency
Max
SDA_IN
SDA_IN
CLOCK
CLOCK
SDA
SDA
SCL
SCL
Figure 15-10. Bus Error Interrupt Timing
Figure 15-9
(and the interrupt occurs) two clocks after the synchronized
and filtered SDA line transitions to a ‘1’, when the SCL line is
high.
Figure 15-9. Stop Status and Interrupt Timing
Synchronized)
TOP DETECT
Figure 15-10
Bus Error status (and interrupt) occurs one cycle after the
internal Start or Stop detect (two cycles after the filtered and
synchronized SDA input transition).
and STATUS
STOP IRQ
SDA_IN
CLOCK
SDA
SCL
shows the timing for Stop status. This bit is set
illustrates the timing for bus error interrupts.
I2C Slave
131
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