CY8CTST200A-48LTXIT Cypress Semiconductor Corp, CY8CTST200A-48LTXIT Datasheet - Page 236
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CY8CTST200A-48LTXIT
Manufacturer Part Number
CY8CTST200A-48LTXIT
Description
CY8CTST200A-48LTXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-48LTXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
38
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-QFN
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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IDX_PP
21.3.48 IDX_PP
This register is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page PSoC device.
This register is only used when a device has more than one page of SRAM. In the table above, note that reserved bits are
grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a
value of ‘0’. For additional information, refer to the
Bit
2:0
236
Individual Register Names and Addresses:
IDX_PP : 0,D3h
Access : POR
Bit Name
0,D3h
Page Bits[2:0]
Name
Indexed Memory Access Page Pointer Register
7
6
Description
Bits determine which SRAM page an indexed memory access operates on. See the
tions on page 42
000b
001b
010b
011b
100b
101b
110b
111b
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SRAM Page 0
SRAM Page 1
SRAM Page 2
SRAM Page 3
SRAM Page 4
SRAM Page 5
SRAM Page 6
SRAM Page 7
5
Register Definitions on page 42
for more information on when this register is active.
4
0,D3h
3
in the RAM Paging chapter .
2
Page Bits[2:0]
RW : 0
1
Register Defini-
0
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