CYWUSB6935-48LFXI Cypress Semiconductor Corp, CYWUSB6935-48LFXI Datasheet - Page 11
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CYWUSB6935-48LFXI
Manufacturer Part Number
CYWUSB6935-48LFXI
Description
IC,Upconverter And Downconverter,LLCC,48PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CYWUSB6935-48LFXC.pdf
(34 pages)
Specifications of CYWUSB6935-48LFXI
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
DSSS, GFSK
Applications
AMR, ISM, RKE
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1626
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYWUSB6935-48LFXI
Manufacturer:
CY
Quantity:
1 060
Table 9. Receive SERDES Interrupt Enable
Document #: 38-16008 Rev. *E
Bit
Underflow B
7
6
5
4
3
2
1
0
Underflow B
Overflow B
EOF B
Full B
Underflow A
Overflow A
EOF A
Full A
7
Name
Addr: 0x07
Overflow B
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when
it is empty.
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg
0x0B) before the prior data is read out.
The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
1 = EOF B interrupt enabled for Channel B Receiver
0 = EOF B interrupt disabled for Channel B Receiver
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field.
If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is
cleared by reading the receive status register
The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B)
having data placed in it.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data
B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data A register (Reg 0x09)
1 = Underflow A interrupt enabled for Receive SERDES Data A
0 = Underflow A interrupt disabled for Receive SERDES Data A
An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when
it is empty.
The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data A register (0x09)
1 = Overflow A interrupt enabled for Receive SERDES Data A
0 = Overflow A interrupt disabled for Receive SERDES Data A
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg
0x09) before the prior data is read out.
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel
A Receiver.
1 = EOF A interrupt enabled for Channel A Receiver
0 = EOF A interrupt disabled for Channel A Receiver
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field.
If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared
by reading the receive status register.
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having
data written into it.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data
A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
6
EOF B
5
Full B
REG_RX_INT_EN
4
Underflow A
Description
3
Overflow A
2
EOF A
1
CYWUSB6935
Default: 0x00
Page 11 of 34
Full A
0
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