DAC8512FSZ-REEL7 Analog Devices Inc, DAC8512FSZ-REEL7 Datasheet - Page 4
DAC8512FSZ-REEL7
Manufacturer Part Number
DAC8512FSZ-REEL7
Description
IC,D/A CONVERTER,SINGLE,12-BIT,BICMOS,SOP,8PIN
Manufacturer
Analog Devices Inc
Datasheet
1.DAC8512FSZ.pdf
(20 pages)
Specifications of DAC8512FSZ-REEL7
Settling Time
16µs
Number Of Bits
12
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
2.5mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Channels
1
Resolution
12b
Conversion Rate
62.5KSPS
Interface Type
Serial (3-Wire)
Single Supply Voltage (typ)
5V
Dual Supply Voltage (typ)
Not RequiredV
Architecture
R-2R
Power Supply Requirement
Single
Output Type
Voltage
Integral Nonlinearity Error
2+/- LSB
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
DAC8512
CS
H
L
L
L
H
H
H
H
NOTES
l
2
3
4
CS and CLK are interchangeable.
Returning CS HIGH avoids an additional “false clock” of serial data input.
Do not clock in serial data while LD is LOW.
+
+ positive logic transition; – negative logic transition; X = Don’t Care.
2
CLK
X
L
H
L
X
X
X
X
+
2
V
OUT
CLR
H
H
H
H
H
H
H
L
CLK
CLK
CLR
SDI
SDI
+
CS
LD
LD
FS
ZS
LD
H
H
H
H
H
L
X
H
–
t
ld1
D11
Serial Shift Register Function
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
t
css
D10
CLK
SDI
CS
D9
Figure 2. Equivalent Clock Input Logic
t
cl
Table I. Control-Logic Truth Table
t
ds
D8
Figure 1. Timing Diagram
ESD PROTECTION DIODES TO V
t
dh
D7
t
ch
–4–
D6
D5
DAC Register Function
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with All Zeros
Latched All Zeros
DATA
DD
t
D4
ldw
AND GND
REGISTER
t
s
SHIFT
D3
D2
ERROR BAND
1 LSB
D1
t
csh
D0
t
ld2
t
clrw
t
S
REV. A