DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 8

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F Family Reference Manual
35.3
35.3.1
35.3.2
Figure 35-2:
DS70272B-page 35-8
Note 1: The user application must write transmit data to and read received data from SPI1BUF. The SPI1TXB and
2: Using the SS1 pin in the Slave mode of operation is optional.
8-bit and 16-bit Data Transmission/Reception
Master and Slave Modes
Modes of Operation
SPI1RXB registers are memory mapped to SPI1BUF.
PROCESSOR 1 (SPI Master)
SPI Master/Slave Connection
MSTEN (SPI1CON1<5>) = 1
MSb
Serial Transmit Buffer
Serial Receive Buffer
The SPI module has flexible operating modes, which are discussed in the following sections:
• 8-bit and 16-bit Data Transmission/Reception
• Master and Slave Modes
• Framed SPI Modes
• SPI1 Receive-only Operation
• SPI1 Error Handling
The MODE16 control bit (SPI1CON1<10>) allows the module to communicate in either 8-bit or
16-bit mode. The functionality will be the same for each mode, except for the number of bits that
are received and transmitted. Additionally, the following items should be noted in this context:
• The module is reset when the value of the MODE16 bit is changed. Consequently, the bit
• Data is transmitted out of bit 7 of the SPI1SR register for 8-bit operation, while it is transmit-
• When transmitting or receiving data, 8 clock pulses at the SCK1 pin are required to shift
Data can be thought of as taking a direct path between the Most Significant bit (MSb) of one
module’s shift register and the Least Significant bit (LSb) of the other, and then into the
appropriate Transmit or Receive Buffer. The module configured as the master module provides
the serial clock and synchronization signals (as required) to the slave device. Figure 35-2 shows
the connection of the Master and Slave modules.
Shift Register
(SPI1BUF)
should not be changed during normal operation.
ted out of bit 15 for 16-bit operation. In both modes, data is shifted into bit 0 of the SPI1SR
register.
data in or out in 8-bit mode, while 16 clock pulses are required in 16-bit mode.
SPI1 Buffer
(SPI1RXB)
(SPI1TXB)
(SPI1SR)
(1)
LSb
SDO1
SCK1
SDI1
SS1
Serial Clock
SSEN (SPI1CON1<7>) = 1 and MSTEN (SPI1CON1<5>) = 0
SDI1
SDO1
SCK1
SS1
(2)
MSb
PROCESSOR 2 (SPI Slave)
Serial Transmit Buffer
Serial Receive Buffer
Shift Register
(SPI1BUF)
(SPI1RXB)
(SPI1TXB)
SPI1 Buffer
(SPI1SR)
© 2008 Microchip Technology Inc.
(1)
LSb