DSPIC33EP256MU810-I/PT Microchip Technology, DSPIC33EP256MU810-I/PT Datasheet - Page 158

• Manufacturer Part Number: DSPIC33EP256MU810-I/PT
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 280KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 8-12:
DS70616E-page 158
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
RQCOL7
U-0
R-0
—
Unimplemented: Read as ‘0’
RQCOL14: Channel 14 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL13: Channel 13 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL12: Channel 12 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL11: Channel 11 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL10: Channel 10 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL9: Channel 9 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL8: Channel 8 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL7: Channel 7 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL6: Channel 6 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL5: Channel 5 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL4: Channel 4 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL3: Channel 3 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
RQCOL14
RQCOL6
R-0
R-0
DMARQC: DMA REQUEST COLLISION STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
RQCOL13
RQCOL5
R-0
R-0
RQCOL12
RQCOL4
R-0
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RQCOL11
RQCOL3
R-0
R-0
RQCOL10
RQCOL2
R-0
R-0
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
RQCOL9
RQCOL1
R-0
R-0
RQCOL8
RQCOL0
R-0
R-0
bit 8
bit 0