DSPIC33FJ06GS101-I/P Microchip Technology, DSPIC33FJ06GS101-I/P Datasheet - Page 191
DSPIC33FJ06GS101-I/P
Manufacturer Part Number
DSPIC33FJ06GS101-I/P
Description
16 Bit MCU/DSP 40MIPS 6 KB FLASH SMPS 18 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
Specifications of DSPIC33FJ06GS101-I/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
6KB (6K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 12-2:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit
TON
R/W-0
U-0
—
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits
(2)
must be cleared to operate the 32-bit timer in Idle mode.
have no effect.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
TON: Timery On bit
1 = Starts 16-bit Timer
0 = Stops 16-bit Timer
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1 = Discontinue timer operation when device enters Idle mode
0 = Continue timer operation in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timer
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
TCKPS<1:0>: Timer
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Unimplemented: Read as ‘0’
TCS: Timer
1 = External clock from TxCK pin
0 = Internal clock (F
Unimplemented: Read as ‘0’
TGATE
R/W-0
U-0
—
TyCON: TIMER CONTROL REGISTER (y = 3)
(2)
y
Clock Source Select bit
W = Writable bit
y
‘1’ = Bit is set
Gated Time Accumulation Enable bit
TSIDL
R/W-0
R/W-0
(2)
OSC
TCKPS<1:0>
y
y
y
Input Clock Prescale Select bits
(1)
/2)
(1)
R/W-0
U-0
(2)
Preliminary
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(2)
(2)
U-0
U-0
—
—
x = Bit is unknown
TCS
R/W-0
U-0
—
(2)
DS70318D-page 189
U-0
U-0
—
—
bit 8
bit 0
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