DSPIC33FJ128GP204-E/PT Microchip Technology, DSPIC33FJ128GP204-E/PT Datasheet - Page 135
![16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC33FJ128GP204-E/PT
Manufacturer Part Number
DSPIC33FJ128GP204-E/PT
Description
16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP204-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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REGISTER 8-5:
REGISTER 8-6:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
Note 1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
R/W-0
R/W-0
R/W-0
U-0
—
2:
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
Number of DMA transfers = CNT<9:0> + 1.
PAD<15:0>: Peripheral Address Register bits
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits
R/W-0
R/W-0
R/W-0
U-0
—
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
‘1’ = Bit is set
‘1’ = Bit is set
W = Writable bit
W = Writable bit
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
CNT<7:0>
PAD<15:8>
PAD<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
R/W-0
R/W-0
R/W-0
(2)
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
CNT<9:8>
DS70292E-page 135
(1)
R/W-0
R/W-0
R/W-0
(2)
R/W-0
bit 8
bit 0
bit 8
bit 0
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