DSPIC33FJ128GP204T-I/ML Microchip Technology, DSPIC33FJ128GP204T-I/ML Datasheet - Page 267
![16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128GP204T-I/ML
Manufacturer Part Number
DSPIC33FJ128GP204T-I/ML
Description
16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP204T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128GP204T-I/MLTR
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REGISTER 22-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-9
bit 8
bit 7
bit 6-0
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DACEN
R/W-0
U-0
—
DACEN: DAC1 Enable bit
1 = Enables module
0 = Disables module
Unimplemented: Read as ‘0’
DACSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
AMPON: Enable Analog Output Amplifier in Sleep Mode/Stop in Idle Mode bit
1 = Analog Output Amplifier is enabled during Sleep Mode/Stop in Idle mode
0 = Analog Output Amplifier is disabled during Sleep Mode/Stop in Idle mode
Unimplemented: Read as ‘0’
FORM: Data Format Select bit
1 = Signed integer
0 = Unsigned integer
Unimplemented: Read as ‘0’
DACFDIV<6:0>: DAC Clock Divider bit
1111111 = Divide input clock by 128
•
•
•
0000101 = Divide input clock by 6 (default)
•
•
•
0000010 = Divide input clock by 3
0000001 = Divide input clock by 2
0000000 = Divide input clock by 1 (no divide)
R/W-0
U-0
—
DAC1CON: DAC CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
DACSIDL
R/W-0
R/W-0
AMPON
R/W-0
R/W-0
DACFDIV<6:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
R/W-1
U-0
—
x = Bit is unknown
R/W-0
U-0
—
DS70292E-page 267
FORM
R/W-0
R/W-1
bit 8
bit 0
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