DSPIC33FJ12MC202-E/ML Microchip Technology, DSPIC33FJ12MC202-E/ML Datasheet - Page 79
![12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ12MC202-E/ML
Manufacturer Part Number
DSPIC33FJ12MC202-E/ML
Description
12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
Specifications of DSPIC33FJ12MC202-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
APPENDIX E:
Revision C (June 2006)
• Added code protection Configuration register
• Added information about Unit ID
• Added ERASES, ERASEG and ERASEC
• Added checksum computation equation
Revision D (March 2007)
• Added information specific to the
• Added specific checksum computations for all
• Updated ICSP bulk/page erase and row/byte
• Added the P20 timing characteristic
• Updated timing characteristics and references to
• Updated the ICSP code examples
© 2010 Microchip Technology Inc.
descriptions
programming executive commands
dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/
202 and PIC24HJ12GP201/202 devices in sev-
eral sections, including pinout diagrams, program
memory sizes and Device ID values
dsPIC33F and PIC24H devices
program code examples to show externally timed
operation (waiting for specific delay periods)
the timing characteristics
REVISION HISTORY
Revision E (June 2007)
• Removed list of devices from first page. This
• Added information specific to the following new
• Updated paragraph in
• Renamed Table 2-1 to “Pins Used During
• Reordered list of devices in Table 2-2, Table 3-2
• Removed all pin diagrams
• Updated checksum information in Table 3-2 for
• Added a Note to
• Changed bit 5 of the FOSCSEL register to
• Modified the first paragraph of
• Added
document covers all released dsPIC33F/PIC24H
devices, therefore, references to specific devices
are included when applicable
devices in several sections, including program
memory sizes, Configuration bit descriptions,
checksum computations, Configuration registers,
and Device ID values:
- dsPIC33FJ32GP202
- dsPIC33FJ32GP204
- dsPIC33FJ16GP304
- dsPIC33FJ32MC202
- dsPIC33FJ32MC204
- dsPIC33FJ16MC304
- PIC24HJ32GP202
- PIC24HJ32GP204
- PIC24HJ16GP304
During Programming”
location of complete pin diagrams
Programming”
and Table 7-1 by device family and memory size
the following devices:
- dsPIC33FJ12GP201
- dsPIC33FJ12GP202
- dsPIC33FJ12MC201
- dsPIC33FJ12MC201
- PIC24HJ12GP201
- PIC24HJ12GP202
unimplemented ( — ) in Table 3-4
“Programming Methodology”
Appendix A: “Hex File Format”
Section 3.6.1 “Overview”
Section 2.3 “Pins Used
to include reference to
Section 3.6.2
DS70152H-page 79