DSPIC33FJ16GP102-E/SO Microchip Technology, DSPIC33FJ16GP102-E/SO Datasheet - Page 108
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DSPIC33FJ16GP102-E/SO
Manufacturer Part Number
DSPIC33FJ16GP102-E/SO
Description
16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16GP102-E/SO
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (0.295", 7.50mm Width)
Lead Free Status / Rohs Status
Details
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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
8.1
The
dsPIC33FJ16MC101/102
system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with 4x PLL
• Primary (MS, HS or EC) Oscillator
• Primary Oscillator with 4x PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
8.1.1
8.1.1.1
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The FRC frequency depends on the FRC accuracy
(see
Tuning register (see
8.1.1.2
The primary oscillator can use one of the following as
its clock source:
• MS (Crystal): Crystals and ceramic resonators in
• HS (High-Speed Crystal): Crystals in the range of
• EC (External Clock): The external clock signal is
8.1.1.3
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
8.1.1.4
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
DS70652C-page 108
the range of 4 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
10 MHz to 32 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
directly applied to the OSC1 pin.
Table
CPU Clocking System
26-18) and the value of the FRC Oscillator
SYSTEM CLOCK SOURCES
Fast RC
Primary
Secondary
Low-Power RC
dsPIC33FJ16GP101/102
Register
devices
8-3).
provide
seven
and
Preliminary
8.1.1.5
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip 4x
Phase-Locked Loop (PLL) to provide faster output
frequencies for device operation. PLL configuration is
described in
8.1.2
The oscillator source used at a device Power-on
Reset event is selected using Configuration bit
settings. The oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to
Bits”
Selection
(FOSCSEL<2:0>), and the Primary Oscillator Mode
Select
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. The FRC primary oscillator is
the default (unprogrammed) selection.
The Configuration bits allow users to choose among 12
different clock modes, shown in
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) F
generate the device instruction clock (F
peripheral clock time base (F
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJ16GP101/102
and dsPIC33FJ16MC101/102 architecture.
Instruction execution speed or device operating
frequency, F
EQUATION 8-1:
for further details.) The Initial Oscillator
Configuration
SYSTEM CLOCK SELECTION
CY
Section 8.1.3 “PLL
PLL
Configuration
, is given by:
F
CY
DEVICE OPERATING
FREQUENCY
Section 23.1 “Configuration
© 2011 Microchip Technology Inc.
=
F
-------------
bits,
OSC
2
bits,
Table
P
Configuration”.
OSC
). F
is divided by 2 to
8-1.
CY
POSCMD<1:0>
FNOSC<2:0>
CY
defines the
) and the
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