DSPIC33FJ16GS404T-I/ML Microchip Technology, DSPIC33FJ16GS404T-I/ML Datasheet - Page 250
![16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ16GS404T-I/ML
Manufacturer Part Number
DSPIC33FJ16GS404T-I/ML
Description
16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS404T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ06GS101-ISO PDF datasheet
- DSPIC33FJ06GS101-ISO PDF datasheet #2
- DSPIC33FJ06GS101-ISO PDF datasheet #3
- Current page: 250 of 346
- Download datasheet (6Mb)
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-3:
REGISTER 19-4:
DS70318D-page 248
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-1
bit 0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12
bit 11-0
Note:
Note 1: The encoding results are shifted left two bits so bits 1-0 of the result are always zero.
PCFG7
R/W-0
R/W-0
R/W-0
U-0
—
2: As an alternative to using the ADBASE Register, the ADCP0-6 ADC Pair Conversion Complete Interrupts
Not all PCFGx bits are available on all devices. See Figure 19-1 through Figure 19-6 for the available
analog pins (PCFGx = ANx, where x = 0-11).
can be used to invoke A to D conversion completion routines for individual ADC input pairs.
ADBASE<15:1>: This register contains the base address of the user’s ADC Interrupt Service Routine
jump table. This register, when read, contains the sum of the ADBASE register contents and the
encoded value of the PxRDY status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the
highest priority, and P6RDY is the lowest priority.
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
PCFG<11:0>: A/D Port Configuration Control bits
1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AV
0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage
PCFG6
R/W-0
R/W-0
R/W-0
U-0
—
ADBASE: A/D BASE REGISTER
ADPCFG: A/D PORT CONFIGURATION REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
PCFG5
R/W-0
R/W-0
R/W-0
U-0
—
ADBASE<7:1>
PCFG4
R/W-0
R/W-0
R/W-0
U-0
Preliminary
ADBASE<15:8>
—
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
(1,2)
PCFG11
PCFG3
R/W-0
R/W-0
R/W-0
R/W-0
(1,2,3,4)
PCFG10
PCFG2
R/W-0
R/W-0
R/W-0
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
PCFG9
PCFG1
R/W-0
R/W-0
R/W-0
R/W-0
PCFG8
PCFG0
R/W-0
R/W-0
R/W-0
SS
U-0
—
bit 8
bit 0
bit 8
bit 0
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